JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech II Year DIGITAL ELECTRONICS Previous Question Paper (February - 2024 - R22)

B.Tech | II Year | I Semester | R22 | February - 2024

Answer PaperPaper Code: 183APMaximum Marks: 60Time: 3 Hours

Part-A is a compulsory question. Part-B consists of ten questions; the student should answer one from each pair. Hence, the student should answer five questions from Part-B.

PART - A

Compulsory Question

1

Answer all sub-questions:

10 marks
a

Find the equivalent Gray code for [10110]₂.

1 marks

Answer

To convert the binary number 10110 to Gray code, the Most Significant Bit (MSB) is copied down. Subsequent bits are obtained by performing an XOR operation between the current binary bit and the previous binary bit.

  • Binary: 1 0 1 1 0
  • Gray MSB: 1
  • Next bits: 1⊕0=1, 0⊕1=1, 1⊕1=0, 1⊕0=1

The resulting Gray code is:

11101
b

Outline the concept of duality in Boolean algebra.

1 marks

Answer

The Principle of Duality states that any Boolean identity remains valid if the operators (AND and OR) are interchanged and the identity elements (0 and 1) are swapped. If an expression is true, its dual is also true.

c

What are don’t care terms?

1 marks

Answer

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d

Prove that the logical sum of all minterms of a Boolean function of 2 variables is 1.

1 marks

Answer

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e

How does a 1-bit comparator work?

1 marks

Answer

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f

State the concept of parallel binary adder.

1 marks

Answer

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g

Mention any two differences between the edge triggering and level triggering.

1 marks

Answer

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h

What is sequential circuit? Give some example.

1 marks

Answer

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i

Distinguish between critical race and non-critical race.

1 marks

Answer

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j

List the different techniques used in State assignment.

1 marks

Answer

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PART - B

210 marks
a

Minimize the following Boolean expressions using Boolean Algebra and draw the logic diagram:

X'Y'Z + X'YZ + XY'

5 marks

Answer

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b

Perform the BCD addition of 375 and -267.

5 marks

Answer

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OR
310 marks
a

What are universal logic gates? Implement Ex-OR gate using Universal Logic gates.

5 marks

Answer

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b

Obtain 3 level NOR – NOR implementation of:

f = (ab + cd)ef

5 marks

Answer

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4

Using K-map method, Simplify the following Boolean function and obtain (a) minimal SOP and (b) minimal POS expression & realize using only NAND and NOR gates:

F = ∑m(0,2,3,6,7) + d(8,10,11,15)

10 marks

Answer

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OR
5

Simplify the following function using K – map,

f = ABCD + AB'C'D' + AB'C + AB
and realize the SOP using only NAND gates and POS using only NOR gates.

10 marks

Answer

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610 marks
a

Draw and explain the operation of full adder.

5 marks

Answer

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b

Explain the operation of 4×1 multiplexer using suitable diagram.

5 marks

Answer

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OR
7

Draw the logic diagram of BCD to Decimal decoder and explain its operations.

10 marks

Answer

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8

Design a synchronous 3-bit counter which counts in the sequence 1, 3, 2, 6, 7, 5, 4 using T FF.

10 marks

Answer

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OR
9

Draw the logic diagram for a 5- bit serial load shift register using D FF and explain.

10 marks

Answer

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1010 marks
a

Classify the methods of Race Free State assignment and explain in detail.

5 marks

Answer

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b

Explain the different methods of state assignment.

5 marks

Answer

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OR
11

Design a clocked sequential machine using JK flip flops for the state diagram. Use state reduction if possible and make proper state assignment.

10 marks

Answer

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About this paper

This page contains the solved question paper with answers of DIGITAL ELECTRONICS from JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD for B.Tech CSE(IoT) II Year I Semester, February - 2024, R22.

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