JNTU
JNTU B.Tech II DIGITAL LOGIC DESIGN Previous Question Paper (February - 2024 - R13)
Note: i) Question paper consists of Part A, Part B. ii) Part A is compulsory, which carries 25 marks. In Part A, answer all questions. iii) In Part B, Answer any one question from each unit. Each question carries 10 marks and may have a, b as sub questions.
PART - A
What are 2’s complement and 9’ s complement of a numbers? Give examples.
Answer
The 2's complement of an n-bit binary number is obtained by adding 1 to the 1's complement of the number. It is used to represent signed numbers in digital systems. For example, the 2's complement of 0101 (5) is 1010 + 1 = 1011 (-5).
The 9's complement of a decimal digit is obtained by subtracting each digit of the number from 9. It is used to facilitate subtraction in decimal arithmetic. For example, the 9's complement of 456 is calculated as (999 - 456) = 543.
State and prove De Morgan theorems.
Answer
De Morgan's theorems are fundamental laws in Boolean algebra used to simplify logic expressions and convert between different logic gate types. The two theorems are:
- The complement of a product is equal to the sum of the complements: (A ⋅ B)' = A' + B'
- The complement of a sum is equal to the product of the complements: (A + B)' = A' ⋅ B'
To prove these theorems, we use a truth table to show that the left-hand side (LHS) and right-hand side (RHS) produce identical outputs for all possible input combinations of A and B.
| A | B | A ⋅ B | (A ⋅ B)' | A' | B' | A' + B' |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 1 | 1 | 1 |
| 0 | 1 | 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 | 1 | 1 |
| 1 | 1 | 1 | 0 | 0 | 0 | 0 |
Since the column for (A ⋅ B)' is identical to the column for A' + B', the first theorem is proved. A similar truth table approach confirms the second theorem by showing (A + B)' equals A' ⋅ B'.
What is the use of don’t care combinations?
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Write the canonical form of the following expression: F (A, B, C, D) = A′ + BC + CD′.
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Draw the logic diagram for 4×2 encoder.
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Can more than one decoder output be activated at one time? Justify your answer?
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What is race around condition? How it is avoided?
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Show the excitation table of JK flip flop.
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What are shift micro operations and what are the different types?
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Draw the memory hierarchy in terms of capacity and access time.
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PART - B
i) Convert 110001.1010010 into hexadecimal. ii) Convert (423.25)10 into Hex.
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Explain about even and odd parity check with an example, what is the drawback?
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Simplify the following Boolean expressions to a minimum number of literals i) ABC+A'B+ABC' ii) xy + x(wz+wz').
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Derive the hamming code for the sequence (101011).
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Simplify the following Boolean functions, using a four variable Karnaugh map method and implement the simplified function using NAND gates F(A,B,C,D) = ∑ (0,2,4,5,6,7,8,10,13,15).
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Implement the function f(a,b,c)=∑(1,3,4,6) using NOR-NOR two level gate structure.
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Obtain the simplified expression in product of sums. F(A,B,C,D) = π(1,3,5,7,13,15).
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Realize the following function Y = A + BCD using NAND gates only.
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What is a combinational logic circuit? Implement a Full adder using two half adders and one OR gate.
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Define a multiplexer? Draw a 4:1 multiplexer for the function f(a,b,c,d)=∑(0, 4,5,10,11,12,15).
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Implement an odd parity generator for 3-bit using a decoder.
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Explain a binary parallel adder with look ahead carry scheme.
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Design a 4-bit universal shift register and explain its operation?
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Design a mealy type sequence detector to detect a serial input sequence of 101.
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Draw the circuit diagram of a 4 bit UP/DOWN binary counter and explain its working with the help of its state diagram and truth table.
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What is Cache memory? Explain the organization of cache memory with suitable diagrams.
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Implement the following Boolean functions using PLA with 3 AND gates. F1 (ABC) = ∑ (3,5,7), F2 = ∑(4,5,7).
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With a neat diagram, explain in detail about two-dimensional memory decoding scheme.
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