JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech II SWITCHING THEORY AND LOGIC DESIGN Previous Question Paper (April/May - 2018 - R13)
Note: This question paper contains two parts A and B. Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit. Each question carries 10 marks and may have a, b, c as sub questions.
PART-A
Prove (A*B) + ( A + B) = 1.
Answer
(A·B) + (A' + B') = A·B + (A·B)' = 1. This follows from the complement law X + X' = 1, where X = A·B.
Prove that OR-AND network is equivalent to NOR-NOR network.
Answer
An OR-AND network implements F = (A+B)·(C+D). By applying De Morgan's Law to each term and the entire expression, we get F = ((A+B)' + (C+D)')' = (A'·B' + C'·D')'. This is equivalent to a NOR-NOR structure where the inputs are inverted before the first NOR stage and the output is inverted by a second NOR stage (acting as an inverter).
Simplify the Boolean function F(X,Y,Z)=∑m(3,4,6,7) using K-map.
Answer
Sign in to view the complete answer paper.
Mention the hazards in combinational circuits.
Answer
Sign in to view the complete answer paper.
Compare combinational and sequential circuits.
Answer
Sign in to view the complete answer paper.
Draw the circuit to convert JK Flip Flop to T Flip Flop.
Answer
Sign in to view the complete answer paper.
Define State Table and State Diagram.
Answer
Sign in to view the complete answer paper.
Compare asynchronous and synchronous counters.
Answer
Sign in to view the complete answer paper.
Define ASM Chart.
Answer
Sign in to view the complete answer paper.
What are the capabilities and limitations of FSMs?
Answer
Sign in to view the complete answer paper.
PART-B
What are Universal Gates? Realize all the logic gates using NAND.
Answer
Sign in to view the complete answer paper.
Convert the following (527)10 = (?) Gray = (?) BCD = (?), XS-3.
Answer
Sign in to view the complete answer paper.
Generate the hamming code for the data 1101.
Answer
Sign in to view the complete answer paper.
Reduce the following Boolean expression using theorems: F = A′B′C+ABC+A′BC+ABC′+A′B′C′
Answer
Sign in to view the complete answer paper.
Design the logic circuit that coverts 4 bit binary data to gray code.
Answer
Sign in to view the complete answer paper.
Simplify the following expressions using K-Map and realize with NAND gates: F = ∑m (0,2,5,9,15) + ∑d(6,7,8,10,12,13)
Answer
Sign in to view the complete answer paper.
Define an Implicant, Prime Implicant, Essential Prime Implicants.
Answer
Sign in to view the complete answer paper.
Explain the practical aspects related to combinational logic design.
Answer
Sign in to view the complete answer paper.
Design a Full adder using 4×1 MUX.
Answer
Sign in to view the complete answer paper.
What is race around condition in JK Flip Flop and how it can be controlled.
Answer
Sign in to view the complete answer paper.
Design SR Flip Flop using JK-Flip Flop.
Answer
Sign in to view the complete answer paper.
Explain in detail about timing and triggering considerations in sequential circuits.
Answer
Sign in to view the complete answer paper.
Design and explain a synchronous MOD-13 down-counter using j-k flipflop.
Answer
Sign in to view the complete answer paper.
Design and explain a 4-bit ring counter using D-flip flops with relevant timing diagrams.
Answer
Sign in to view the complete answer paper.
Write short notes on synchronous sequential finite state machines.
Answer
Sign in to view the complete answer paper.
Explain the design of ring counter using shift registers.
Answer
Sign in to view the complete answer paper.
Draw the timing diagram of 2-bit synchronous counter with negative edge clock.
Answer
Sign in to view the complete answer paper.
Differentiate between Mealy and Moore machine with examples.
Answer
Sign in to view the complete answer paper.
Explain the procedure for state minimization using the partition technique.
Answer
Sign in to view the complete answer paper.
Name the elements of an ASM chart and define each one of them.
Answer
Sign in to view the complete answer paper.
Explain the procedure for state minimization using merger graph and merger table.
Answer
Sign in to view the complete answer paper.