JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech II DIGITAL DESIGN USING VERILOG HDL Previous Question Paper (May - 2019 - R15)
Note: This question paper contains two parts A and B. Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit. Each question carries 10 marks and may have a, b, c as sub questions.
Part A
What is concurrency?
Answer
Concurrency refers to the execution of multiple statements or blocks of code simultaneously. In Verilog, all always and initial blocks execute in parallel, reflecting the physical nature of hardware where components operate concurrently.
What are the white space characters?
Answer
White space characters are used to improve code readability and are ignored by the Verilog compiler. These include spaces, tabs, newlines, form feeds, and carriage returns.
Describe array of instances of primitives.
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Why net delay is needed.
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How is procedure assignment characterized?
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How if and if – else constructs?
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What are bidirectional gates?
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What is mean by module paths?
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What are advantages and limitations feedback model of sequential circuit.
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How combinational circuit can be tested?
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Part B
What are the different models of verilog HDL programming explain them with suitable examples.
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Explain identifiers, comments and strings in verilog.
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Give details of strengths in Verilog.
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Prepare a full – adder module using half – adder module and OR gate primitive in verilog.
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Prepare a module to add 2 BCD numbers in verilog HDL.
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Design a J-K Flip-Flop using NAND gates. Write verilog module for this.
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How to introduce delays in verilog HDL programming? Why these are needed.
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Explain functional bifurcation with example.
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Prepare design module for the following operation and also prepare a suitable test bench and test the design module 2 decimal numbers each of two digits.
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Compare blocking and non-blocking Assignments.
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Prepare design module for the following operation. Prepare a suitable test bench and test the design module. Interrupt service routine (ISR) : An ISR receives an interrupt request (IRQ). The PC content is saved on a stack – 4 bytes deep. Then a specific byte 5a5ah is loaded into the PC. The ISR sets an INTA flag high and returns. Use the ‘wait’ construct and design the module.
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Explain strength contention with trireg nets.
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Implement NAND, AND, OR gates using MOS switches ; test it with a suitable test – bench.
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Implement a pseudo – NMOS 4 – input NOR logic gate. Write a test – bench and test it.
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What are the user defind primitives and write any program using these.
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Explain capacitive model of a sequential circuit and compare it with other models.
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What are the basic differences between sequential circuit testing and combinational circuit testing?
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What is test bench? Why it is needed.
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