Jawaharlal Nehru Technological University Hyderabad

Jawaharlal Nehru Technological University Hyderabad B. Tech III VLSI DESIGN Previous Question Paper (February - 2023 - R18)

B. Tech | III | II | R18 | February - 2023

Answer PaperPaper Code: 156DFMaximum Marks: 75Time: 3 Hours

i) Question paper consists of Part A, Part B. ii) Part A is compulsory, which carries 25 marks. In Part A, Answer all questions. iii) In Part B, Answer any one question from each unit. Each question carries 10 marks and may have a, b as sub questions.

Part A

1.a

Define threshold voltage.

2 marks

Answer

The threshold voltage (Vth) is the minimum gate-to-source voltage (VGS) required to create a conducting inversion layer (channel) between the source and drain terminals of a MOSFET. When VGS is less than Vth, the device is in the cut-off region; when VGS exceeds Vth, the transistor enters the strong inversion region, allowing significant current to flow.

1.b

What is pass transistor and write its advantages.

3 marks

Answer

A pass transistor is a MOSFET used as a switch to pass or block logic signals between nodes in a digital circuit. It operates by connecting the drain to the input signal and the source to the output node, with the gate controlled by a clock or logic signal. When the gate voltage is high (for an NMOS), the transistor conducts, allowing the input signal to pass to the output; when low, it acts as an open circuit.

The advantages of using pass transistors include:

  • Reduced Transistor Count: Logic functions such as multiplexers and XOR gates can be implemented with fewer transistors compared to standard CMOS logic, leading to smaller silicon area.
  • Lower Power Consumption: Due to the reduced number of transistors and lower parasitic capacitance, the overall power dissipation of the circuit is significantly decreased.
  • Higher Speed: The reduced input capacitance and simplified circuit topology allow for faster switching transitions in specific logic applications.
1.c

Draw the layout diagram for NMOS inverter.

2 marks

Answer

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1.d

Compare stick and layout diagrams.

3 marks

Answer

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1.e

What are the different inverter delays?

2 marks

Answer

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1.f

Explain Domino Logic.

3 marks

Answer

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1.g

Compare the SRAM and DRAM.

2 marks

Answer

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1.h

Write the applications of parity circuits.

3 marks

Answer

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1.i

How the CPLD is different from FPGA.

2 marks

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1.j

Compare various simple PLDs.

3 marks

Answer

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Part B

2

What are the different pull ups and explain their working with neat circuit diagram and also compare them.

10 marks

Answer

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OR
310 marks
a

Analyze the behaviour of CMOS inverter.

5 marks

Answer

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b

Derive the value of Zpu/Zpd of inverter driven by another inverter.

5 marks

Answer

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4

Explain the various steps involved in VLSI design flow in detail.

10 marks

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OR
5

Draw the NMOS stick diagram for the following Boolean expression: 𝑓 = 𝐴 + 𝐵𝐶.

10 marks

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6

Describe about the choice of fan – in and fan – out selection in gate level design.

10 marks

Answer

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OR
7

Design and explain the switch logic implementation for a four way multiplexer.

10 marks

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8

Compare various memories in detail with architectures.

10 marks

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OR
9

Design a 4-bit magnitude comparator and draw its layout.

10 marks

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10

Explain the architecture of FPGA and what are the advantages of FPGA?

10 marks

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OR
11

Explain chip level test techniques with techniques.

10 marks

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