JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B. Tech IV Year ANALOG CMOS IC DESIGN Previous Question Paper (September - 2020 - R16)

B. Tech | IV Year | II Semester | R16 | September - 2020

Answer PaperPaper Code: 138AQMaximum Marks: 75Time: 2 Hours

Answer any Five Questions

All Questions Carry Equal Marks

Main

115 marks
a

How to construct a resistor using MOS transistor?

10 marks

Answer

A MOS transistor can be configured to act as a resistor by operating it in the triode (linear) region. This is achieved by ensuring the drain-to-source voltage is small compared to the overdrive voltage, specifically VDS < VGS - VTH.

The drain current in the linear region is given by:

ID = μnCox(W/L)[(VGS - VTH)VDS - (VDS2/2)]

For small values of VDS, the quadratic term (VDS2/2) becomes negligible, simplifying the expression to:

ID ≈ μnCox(W/L)(VGS - VTH)VDS

The equivalent resistance Ron is defined as VDS/ID:

Ron = 1 / [μnCox(W/L)(VGS - VTH)]

To implement this in circuits:

  • Voltage-Controlled Resistor: The resistance is controlled by the gate voltage VGS. Increasing VGS reduces the resistance.
  • Linearity: To maintain high linearity, VDS must be kept very small.
  • Applications: These are commonly used in continuous-time filters, automatic gain control circuits, and as load elements in CMOS amplifiers.
b

With the help of required expressions explain Sub-threshold MOS Model.

5 marks

Answer

When the gate-source voltage VGS is less than the threshold voltage VTH, the transistor is in the sub-threshold (weak inversion) region. In this regime, the channel is not fully formed, and conduction occurs primarily through diffusion rather than drift.

The drain current in the sub-threshold region is exponentially dependent on VGS, similar to a BJT:

ID = I0 exp[(VGS - VTH) / (n VT)] [1 - exp(-VDS / VT)]

Where:

  • I0 is a process-dependent constant.
  • VT is the thermal voltage (kT/q ≈ 26 mV at room temperature).
  • n is the sub-threshold swing parameter (typically 1 < n < 2), representing the capacitive voltage divider between the gate oxide and the depletion region.

For VDS > 3VT, the term [1 - exp(-VDS / VT)] approaches unity, and the current becomes independent of VDS, showing a saturation-like behavior. This model is critical for low-power, low-speed CMOS design, such as in watch circuits or medical implants.

215 marks
a

Discuss about current and voltage references and band gap reference in detail with suitable diagrams.

8 marks

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b

Draw the circuit diagram of cascade current mirror.

7 marks

Answer

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315 marks
a

List different types of inverting CMOS amplifiers and draw any one of it.

7 marks

Answer

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b

Draw the High gain amplifier architecture and explain its working.

8 marks

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415 marks
a

What is beta helper? How it used in current mirrors?

7 marks

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b

Design a differential amplifier using CMOS transistors and explain its working.

8 marks

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515 marks
a

Explain the method of calculation of power supply rejection ratio of two stage Op Amp.

10 marks

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b

What are the advantages of two-stage Op-Amp?

5 marks

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6

List various compensation techniques of Op Amps, explain feed forward compensation.

15 marks

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7

Explain the following terms with neat sketch:

15 marks
a

Switched capacitor comparators.

7 marks

Answer

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b

Regenerative comparators.

8 marks

Answer

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8

Define discrete – time comparators and derive the expression for output voltage of switched capacitor comparator.

15 marks

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About this paper

This page contains the question paper of ANALOG CMOS IC DESIGN from JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD for B. Tech ECE IV Year II Semester, September - 2020, R16.

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