JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech IV LOW POWER VLSI DESIGN Previous Question Paper (July/August - 2022 - R18)

B.Tech | IV | II | R18 | July/August - 2022

Answer PaperPaper Code: 158BHMaximum Marks: 75Time: 3 Hours

Answer any five questions

All questions carry equal marks

Main

115 marks
a

Discuss the need of a low power designs in VLSI circuits.

5 marks

Answer

The demand for low power design in VLSI circuits is primarily driven by the need for increased integration density, portability, and reliability. As the number of transistors on a chip grows, power consumption increases, leading to thermal management challenges and the requirement for expensive cooling systems. For mobile devices, power consumption directly dictates battery life, making efficiency critical. Furthermore, high power dissipation leads to increased junction temperatures, which accelerates degradation mechanisms like electromigration and hot-carrier injection, thereby reducing the operational lifespan and reliability of the device.

b

Derive the equation for threshold voltage of a MOSFET and discuss the factors involved in it.

5 marks

Answer

The threshold voltage (Vth) of a MOSFET is the gate-source voltage required to create a conductive channel. It is defined by the following expression:

Vth = Vfb + 2φf + (√2εs q NA (2φf)) / Cox

The factors influencing Vth include:

  • Flat-band voltage (Vfb): Determined by the work function difference between the gate and the substrate and the presence of oxide charges.
  • Surface potential (2φf): Dependent on the doping concentration (NA) of the substrate.
  • Oxide capacitance (Cox): Inversely proportional to the gate oxide thickness (tox); thinner oxides reduce Vth.
  • Body effect: If the source-bulk voltage is non-zero, the depletion region charge increases, raising the threshold voltage.
c

Explain how the Vth and Vdd influences the power dissipation.

5 marks

Answer

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2

Discuss with a suitable figure (i) Switching Power Dissipation (ii) Short Circuit Power Dissipation (iii) Glitching Power Dissipation.

15 marks

Answer

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3

Discuss the two basic architectural level measures to reduce the power in VLSI circuits and explain with suitable examples.

15 marks

Answer

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4

Discuss about power reduction by:

15 marks
a

One hot coding

8 marks

Answer

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b

CG granularity.

7 marks

Answer

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515 marks
a

Write down the differences between carry select adders and carry save adders.

5 marks

Answer

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b

Discuss two types of low voltage low power logic styles with suitable examples.

10 marks

Answer

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615 marks
a

Draw the logic circuit of the conventional CMOS full adder and explain about it.

7 marks

Answer

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b

Explain the basic theory, operation and performance evaluation of carry look-ahead Adder.

8 marks

Answer

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715 marks
a

Discuss the types of multiplier architectures and compare them.

5 marks

Answer

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b

Explain about Booth multiplier with neat architectures.

10 marks

Answer

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815 marks
a

Write down differences between 6T and 4T static RAM cells.

6 marks

Answer

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b

With a neat diagram, explain the block diagram of DRAM architecture.

9 marks

Answer

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About this paper

This page contains the question paper of LOW POWER VLSI DESIGN from JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD for B.Tech ECE IV II, July/August - 2022, R18.

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