JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech IV TEST AND TESTABILITY Previous Question Paper (September - 2022 - R18)

A Stuck-at fault is a logic fault model where a signal line in a digital circuit is permanently fixed to a logic value of 0 (Stuck-at-0) or 1 (Stuck-at-1), regardless of the input values applied to the circuit. This model assumes that the fault is independent of the circuit's operation and typically represents physical defects like short circuits to power or ground lines. Testing for these faults involves applying specific test vectors to sensitize the fault path and propagate the incorrect logic value to an observable output.

A Stuck-open fault occurs in CMOS circuits when a transistor fails to conduct, effectively creating an open circuit in the pull-up or pull-down network. Unlike stuck-at faults, this is a sequential fault because it causes the circuit to lose its combinational nature and behave as a memory element by retaining the previous state of the output node. Detecting these faults requires a two-pattern test sequence: the first pattern initializes the output node to a known logic state, and the second pattern attempts to drive the node to the opposite state through the faulty path.