JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech III Year COMPUTER ORGANIZATION Previous Question Paper (August - 2022 - R16)

The CPU contains a set of high-speed storage locations called registers, which are used to hold data, instructions, and addresses during the execution of a program. The primary registers include:

• Program Counter (PC): Holds the memory address of the next instruction to be fetched for execution.
• Instruction Register (IR): Stores the instruction currently being decoded and executed by the CPU.
• Accumulator (AC): A general-purpose register used to store the results of arithmetic and logical operations performed by the Arithmetic Logic Unit (ALU).
• Memory Address Register (MAR): Holds the address of the memory location from which data is to be read or to which data is to be written.
• Memory Data Register (MDR): Contains the data to be written into or read from the addressed memory location.
• General Purpose Registers (R0, R1, ...): Used by the programmer or compiler to store intermediate data and operands during computation.
• Stack Pointer (SP): Maintains the address of the top of the stack in memory, essential for managing function calls and interrupts.
• Status Register (Flags): Contains individual bits (flags) that indicate the outcome of operations, such as Zero (Z), Carry (C), Sign (S), and Overflow (V).

The Control Unit (CU) is the "brain" of the CPU that directs the flow of data and control signals. Its design is primarily categorized into two approaches:

• Hardwired Control Unit: This design uses fixed logic circuits (gates, flip-flops, and decoders) to generate control signals. It is implemented using hardware components, making it extremely fast. However, it is complex to design and lacks flexibility, as any change in the instruction set requires a complete redesign of the hardware.
• Microprogrammed Control Unit: This design uses a control memory to store microinstructions. A control sequence is executed by reading these microinstructions from the control memory. It is highly flexible; the instruction set can be modified by simply updating the microcode in the control memory. While it is slower than hardwired control due to memory access times, it is much easier to design and debug.

The general design process involves identifying the required control signals for each instruction cycle (fetch, decode, execute) and implementing the logic to activate these signals in the correct sequence based on the opcode and status flags.