JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech III LINEAR AND DIGITAL IC APPLICATIONS Previous Question Paper (July - 2023 - R16)
Note: i) Question paper consists of Part A, Part B.
ii) Part A is compulsory, which carries 25 marks. In Part A, Answer all questions.
iii) In Part B, Answer any one question from each unit. Each question carries 10 marks and may have a, b as sub questions.
Part A
Define parameters of Op-Amp: (i) CMRR (ii) Slew rate (iii) Off-set voltage (iv) Large signal voltage gain.
Answer
(i) CMRR (Common Mode Rejection Ratio) is the ratio of differential gain to common-mode gain. (ii) Slew Rate is the maximum rate of change of output voltage per unit time. (iii) Input Offset Voltage is the differential DC voltage required at the input terminals to make the output zero. (iv) Large Signal Voltage Gain is the ratio of output voltage swing to the input voltage required to drive the output to its limits.
Explain the different methods used to increase the input resistance of an op-amp.
Answer
Input resistance can be increased using the following methods:
- Using Bootstrapping: Feeding a portion of the output signal back to the input bias circuitry to minimize the effective voltage drop across input resistors.
- Using FET-input Op-Amps: Utilizing JFET or MOSFET input stages which inherently possess extremely high gate input impedance.
- Using Buffer Amplifiers: Placing a voltage follower (unity gain amplifier) before the main circuit to isolate the source from lower impedance stages.
What are the characteristics of all pass filter and notch filter?
Answer
Sign in to view the complete answer paper.
How does PLL work as frequency multiplier?
Answer
Sign in to view the complete answer paper.
What is the need for A/D and D/A conversion?
Answer
Sign in to view the complete answer paper.
Find the step size and analog output when input is 1000 and 1111. Assume Vref = 5 V.
Answer
Sign in to view the complete answer paper.
Define CMOS Logic levels.
Answer
Sign in to view the complete answer paper.
Draw the circuit diagram of a half subtractor.
Answer
Sign in to view the complete answer paper.
Write about Dynamic RAMs and its applications.
Answer
Sign in to view the complete answer paper.
Discuss how PROM, EPROM and EEPROM technologies differ from each other.
Answer
Sign in to view the complete answer paper.
Part B
Draw the basic block diagram of op-amp and explain the operation of each block.
Answer
Sign in to view the complete answer paper.
Explain the working of a Schmitt trigger with neat circuit diagram.
Answer
Sign in to view the complete answer paper.
Explain the working of non-Inverting amplifier and derive the equation of its Gain.
Answer
Sign in to view the complete answer paper.
Explain the application of three terminal adjustable voltage regulator.
Answer
Sign in to view the complete answer paper.
Design an active high pass filter with cut-off frequency of 4KHz.
Answer
Sign in to view the complete answer paper.
How to generate a sawtooth wave form? Explain the working of such a circuit with neat circuit diagram.
Answer
Sign in to view the complete answer paper.
Explain the operation of Astable multivibrator using 555 timer and also derive the expression for frequency of oscillation.
Answer
Sign in to view the complete answer paper.
Draw the block diagram of 565 PLL and explain about each block. Make circuit connections to track the input signal and explain its operation.
Answer
Sign in to view the complete answer paper.
Draw the block diagram of inverted R-2R DAC and explain its operation in detail.
Answer
Sign in to view the complete answer paper.
With neat schematic, explain the operation of a counter type Analog to Digital converter.
Answer
Sign in to view the complete answer paper.
Draw the circuit of weighted resistor DAC and derive expression for output analog voltage Vo.
Answer
Sign in to view the complete answer paper.
Mention ADC characteristics. Calculate the conversion time for a full-scale input in case of a 12-bit counter type ADC driven by 4 MHz clock.
Answer
Sign in to view the complete answer paper.
Draw the circuit diagram of basic TTL NAND gate and explain the three parts with the help of functional operation.
Answer
Sign in to view the complete answer paper.
Explain about parity generator and checker.
Answer
Sign in to view the complete answer paper.
Draw the dynamic electrical behaviour of CMOS inverter and explain.
Answer
Sign in to view the complete answer paper.
Discuss about 2-input 4-output multiplexer.
Answer
Sign in to view the complete answer paper.
Draw the circuit of a bidirectional shift register with parallel loading using 2 to 4 line decoder and D-flip-flops.
Answer
Sign in to view the complete answer paper.
Design an 8×4 diode ROM using 74×138 for the following data starting from the first location.
Answer
Sign in to view the complete answer paper.
Draw the circuit of MOD 16 Down ripple counter with D-flip-flops and explain its operation.
Answer
Sign in to view the complete answer paper.
With the help of timing waveforms, explain read and write operations of SRAM.
Answer
Sign in to view the complete answer paper.