JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech IV VLSI DESIGN Previous Question Paper (December - 2020 - R16)
Answer any Five Questions. All Questions Carry Equal Marks.
Main
What are the steps involved in IC fabrication? Explain.
Answer
Integrated Circuit (IC) fabrication is a multi-step sequence of photographic and chemical processing steps during which electronic circuits are gradually created on a wafer made of pure semiconducting material, typically silicon. The fundamental steps are as follows:
- Wafer Preparation: High-purity silicon is grown into a cylindrical ingot (Czochralski process) and sliced into thin wafers, which are then polished to a mirror finish to provide a defect-free substrate.
- Oxidation: A thin layer of silicon dioxide (SiO₂) is grown on the wafer surface, usually through thermal oxidation, to act as an insulating layer or a mask for subsequent doping.
- Photolithography: This is the process of transferring a circuit pattern onto the wafer. It involves coating the wafer with a light-sensitive polymer called photoresist, exposing it to ultraviolet light through a photomask, and developing the resist to leave a specific pattern.
- Etching: The exposed areas of the SiO₂ or other layers are removed using chemical etchants (wet etching) or reactive ion plasmas (dry etching) to expose the underlying silicon substrate according to the pattern defined by the photoresist.
- Doping (Diffusion/Ion Implantation): Impurities (dopants like Boron or Phosphorus) are introduced into the silicon to change its electrical conductivity. Ion implantation is the modern standard, where high-energy ions are accelerated into the wafer surface.
- Deposition: Various thin films, such as polysilicon, metal (aluminum or copper), or insulating dielectrics, are deposited onto the wafer using techniques like Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD/Sputtering).
- Metallization: Interconnects are formed by depositing metal layers to create the electrical paths between individual components (transistors, resistors) on the chip.
- Testing and Packaging: After fabrication, individual dies are tested for functionality. Functional dies are then diced from the wafer, mounted into protective packages, and wire-bonded to external pins for integration into electronic systems.
Derive the expression for the threshold voltage of PMOS transistor with and without body effect.
Answer
The threshold voltage Vth of a MOS transistor is the gate-to-source voltage required to create a conducting inversion layer. Without the body effect (i.e., when the source is connected to the bulk, VSB = 0), the threshold voltage is given by:
Where Φms is the work function difference, 2ΦF is the surface potential at strong inversion, and QB0 is the depletion charge density. When a reverse bias voltage VSB is applied between the source and the bulk, the depletion region widens, increasing the charge QB. The threshold voltage with body effect is expressed as:
For a PMOS transistor, the body effect parameter γ is defined as (√(2εsqND)) / Cox. The increase in VSB leads to a more negative threshold voltage for PMOS, effectively making it harder to turn the device on.
Explain the influence of βn/βp in CMOS inverter DC transfer characteristics.
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Why NMOS transistor is selected as pull down transistor? Explain.
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Draw the stick diagram for 2 input NAND gate.
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Explain the lambda based design ruler used for layout.
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Mention the different types of scaling techniques.
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Describe in detail about delay estimation, and transistor sizing with example.
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Describe the fan-in and fan-out characteristics of CMOS with suitable sketches.
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Explain the clocking analysis related to sequential circuits.
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Draw and explain the cross section of a pair of stacked capacitor DRAM cell.
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Discuss the design strategies for CMOS testing.
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