JNTU
JNTU B.Tech III MICROPROCESSORS AND COMPUTER ORGANIZATION Previous Question Paper (December 2018 - R15)
Note: This question paper contains two parts A and B. Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit. Each question carries 10 marks and may have a, b, c as sub questions.
Part A
Write about the Register Organization of 8086 Microprocessor.
Answer
The 8086 microprocessor features 14 internal 16-bit registers, categorized into four groups: General Purpose Registers (AX, BX, CX, DX), Segment Registers (CS, DS, SS, ES), Pointer and Index Registers (SP, BP, SI, DI), and the Status/Instruction Pointer (FLAGS, IP).
Write an 8086 assembly language programme to find factorial of a number.
Answer
MOV AX, 0005H
MOV CX, AX
DEC CX
L1: MUL CX
LOOP L1
MOV RESULT, AXWhat is the use of Interrupt service routine?
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Discuss briefly OS interrupts.
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What is the significance of instruction cycle?
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Explain “Circular shift right and circular shift left” operations.
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Expand and write a short note on instruction “LDA”.
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What is interrupt? If an interrupt occurs, what will be the status of IEN flag bit?
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Is ROM volatile or non volatile memory? Justify.
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Write a short note on DMA.
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Part B
Define memory segmentation and explain the concept of memory segmentation with diagram.
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Write an ALP for 8086 to arrange a list of 16-bit numbers in descending order.
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List and explain the instruction set of 8086 with examples.
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Explain 8086 interrupts and interrupt response with interrupt Vector Table.
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Explain mode-1 and mode-2 operation of 8255.
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Draw and explain the internal architecture of DMA controller.
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List different Arithmetic micro operations. Draw and explain arithmetic circuit along with function table.
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Draw and explain the Arithmetic Logic Shift Unit.
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Explain in brief the RISC architecture.
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Explain the Control unit of basic computer with a neat sketch.
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Explain the Cache memory in detail along with 3 mapping techniques.
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Write a brief note about asynchronous data transfer.
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