JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech II SWITCHING THEORY AND LOGIC DESIGN Previous Question Paper (December - 2018 - R16)
Part A is compulsory. Answer all questions. Part B consists of 5 Units. Answer any one full question from each unit.
Part A
Convert the following numbers with the given radix to decimal: (i) A116 (ii) 617
Answer
(i) A116 = (10 × 161) + (1 × 160) = 160 + 1 = 16110
(ii) 617 = (6 × 71) + (1 × 70) = 42 + 1 = 4310
Represent the following decimal number in BCD: 13597; 99880; 93286.
Answer
BCD representation replaces each decimal digit with its 4-bit binary equivalent:
13597: 0001 0011 0101 1001 0111
99880: 1001 1001 1000 1000 0000
93286: 1001 0011 0010 1000 0110
Find the complements of the following: (i) x'yz' + x'y'z (ii) x(y'z' + yz).
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Implement the function with only NAND gates: F(x,y,z) = Σ(0,6).
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Differentiate combinational and sequential circuits.
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Define clock skew.
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What is state diagram?
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Differentiate asynchronous and synchronous counters.
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Differentiate completely specified and incompletely specified sequential machines.
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Write capabilities and limitations of Finite-State machine.
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Part B - Unit I
Solve for X: (i) (F3A7C2)16 = (X)10 (ii) (2AC5)16 = (10949)X (iii) (0.93)10 = (X)8 (iv) (4057.06)8 = (X)10
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Subtract 27810 from 49510 using the excess-3 subtractor.
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Prove that AB'C + B + BD' + ABD' + A'C = B + C.
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Expand minterms and maxterms for: AB' + ABD' + A + ABC'D.
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Part B - Unit II
Simplify using Boolean postulates and verify using K-map: (x + y' + xy') (xy + x'z + yz)
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Simplify using Boolean postulates and verify using K-map: (A+B) (A'+C) (B+C)
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Realize the expression F=Σm(0,1,3,5,8,11,12,14,15) using 8×1 MUX.
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Design the full adder circuit using two half adder circuits.
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Part B - Unit III
With the block diagram, Truth table, describe the principle operation of edge triggered negative SR flip flop.
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Explain the operation of 4-stage twisted ring counter with circuit diagram and timing diagram.
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With the aid of external logic, convert D type flip-flop to a JK flip-flop.
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Design a synchronous modulo-12 counter using JK flip flops.
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Part B - Unit IV
Design a mod-10 Ripple counter using T flip flops and explain its operation.
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Draw a state diagram of a sequence detector which can detect 101.
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Design a 4 bit ring counter with initial count 1100 loaded in it. Prepare a state table and draw the state diagram including those of unused states and also the output waveforms.
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Part B - Unit V
For the machine shown, find the equivalent partition and a corresponding reduced machine in standard form.
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Design a sequential logic circuit of a 4 bit counter to start counting from 0000 to 1000 and this process should go on. Draw the ASM chart and design the Data processing unit and the control unit.
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