JNTU B.Tech III COMPUTER ORGANIZATION AND OPERATING SYSTEMS Previous Question Paper (November/December - 2020 - R16)

The basic operational concepts of a computer revolve around the interaction between the Central Processing Unit (CPU), Memory, and Input/Output (I/O) units. The CPU contains the Arithmetic Logic Unit (ALU), Control Unit (CU), and registers. The process follows the fetch-decode-execute cycle:

1. Input Unit: Accepts data and instructions from external devices and stores them in memory.
2. Memory Unit: Stores programs and data. It is divided into primary memory (RAM) for fast access and secondary storage for long-term retention.
3. CPU: The Control Unit coordinates the flow of data between units, while the ALU performs arithmetic and logical operations.
4. Output Unit: Sends processed results from the memory to external devices.

The system components are interconnected via a system bus (data, address, and control buses) that facilitates communication between the processor, memory, and I/O modules.

Register transfer and memory transfer are fundamental operations in computer architecture that move data between components.

Register Transfer: This involves moving data between internal processor registers. It is represented by the notation R2 ← R1, meaning the contents of register R1 are transferred into R2. This is typically performed using a common bus system where multiple registers have their outputs connected to a shared bus through multiplexers or tri-state buffers. A control signal selects which register places its data on the bus and which register is enabled to receive it.

Memory Transfer: This involves communication between the CPU and the memory unit. It is divided into two primary operations:

1. Memory Read: The CPU places the memory address on the address bus and asserts the 'Read' control signal. The memory unit then places the data stored at that address onto the data bus, which is subsequently loaded into a CPU register (e.g., MDR).
2. Memory Write: The CPU places the target address on the address bus and the data to be stored on the data bus. It then asserts the 'Write' control signal, causing the memory unit to store the data at the specified location.

These transfers are synchronized by the system clock, ensuring that data is stable on the bus before the receiving register or memory location captures it.