JNTU B.Tech II COMPUTER ORGANIZATION AND MICROPROCESSOR Previous Question Paper (October - 2020 - R18)

An instruction cycle is the sequence of operations performed by the CPU to process a single instruction. It consists of several distinct phases, which repeat continuously as long as the computer is powered on.

1. Fetch Phase: The CPU fetches the instruction from the memory location pointed to by the Program Counter (PC). The instruction is transferred to the Instruction Register (IR), and the PC is incremented to point to the next instruction.
2. Decode Phase: The control unit interprets the opcode stored in the IR to determine the operation to be performed and identifies the required operands.
3. Execute Phase: The CPU performs the actual operation specified by the instruction. This may involve arithmetic or logical operations in the ALU, data movement between registers, or memory access.
4. Store Phase: If the instruction produces a result, it is written back to the destination register or memory location.

Consider the instruction ADD R1, [1000], which adds the value stored at memory address 1000 to the contents of register R1:

• Fetch: The CPU reads the instruction from the memory address held in the PC and loads it into the IR.
• Decode: The control unit identifies the 'ADD' opcode and determines that the operand is located at memory address 1000.
• Execute: The CPU fetches the data from memory address 1000 and sends both the data and the current value of R1 to the ALU for addition.
• Store: The result of the addition is written back into register R1.

Addressing modes in the 8086 microprocessor define how the effective address of an operand is calculated or how the operand itself is specified. The 8086 supports the following primary addressing modes:

1. Immediate Addressing Mode: The operand is specified directly within the instruction. Example:
   MOV AX, 1234H
2. Register Addressing Mode: The operand is held in one of the general-purpose registers. Example:
   MOV AX, BX
3. Direct Addressing Mode: The effective address of the operand is given directly in the instruction as a 16-bit offset. Example:
   MOV AX, [1200H]
4. Register Indirect Addressing Mode: The effective address is held in a base register (BX, BP) or index register (SI, DI). Example:
   MOV AX, [BX]
5. Based Addressing Mode: The effective address is the sum of a base register (BX or BP) and an 8-bit or 16-bit displacement. Example:
   MOV AX, [BX + 05H]
6. Indexed Addressing Mode: The effective address is the sum of an index register (SI or DI) and a displacement. Example:
   MOV AX, [SI + 10H]
7. Based-Indexed Addressing Mode: The effective address is the sum of a base register, an index register, and an optional displacement. Example:
   MOV AX, [BX + SI + 05H]
8. String Addressing Mode: Used for string operations where SI and DI registers point to the source and destination strings. Example:
   MOVSB
9. Relative Addressing Mode: Used in branch instructions, where the target address is calculated by adding an 8-bit signed displacement to the Instruction Pointer (IP). Example:
   JMP LABEL