JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech III Year COMPUTER ORGANIZATION Previous Question Paper (November/December - 2020 - R16)

Memory reference instructions are computer instructions that use the memory address of an operand to perform operations. These instructions typically require at least two memory accesses: one to fetch the instruction from the program counter (PC) address and another to access the operand at the effective address. In a basic computer, memory reference instructions use a 16-bit format where the last 12 bits represent the address, the next 3 bits represent the opcode, and the first bit is the addressing mode bit (I=0 for direct, I=1 for indirect).

Common memory reference instructions include:

• AND (Opcode 000): Performs a logical AND operation between the content of the Accumulator (AC) and the operand at the effective address. The result is stored in the AC.
• ADD (Opcode 001): Adds the content of the memory word at the effective address to the AC. The result is stored in the AC, and the carry bit is stored in E.
• LDA (Opcode 010): Loads the content of the memory word at the effective address into the AC.
• STA (Opcode 011): Stores the content of the AC into the memory word at the effective address.
• BUN (Opcode 100): Branch Unconditionally. It transfers the effective address to the PC, causing the next instruction to be fetched from that address.
• BSA (Opcode 101): Branch and Save Return Address. It stores the current PC value into the memory word at the effective address and then increments the PC to jump to the next instruction.
• ISZ (Opcode 110): Increment and Skip if Zero. It increments the content of the memory word at the effective address. If the result is zero, the PC is incremented by one to skip the next instruction.

Example: Consider the instruction ADD 100 (Hexadecimal 1100). If the I-bit is 0, the processor interprets this as a direct address. It goes to memory location 100, retrieves the data stored there, and adds it to the current value in the AC. If the I-bit were 1, the processor would treat 100 as the address of a pointer, go to address 100 to find the actual effective address, and then perform the addition using the data at that final location.

The 8086 microprocessor contains a 16-bit flag register, of which only 9 bits are active. These flags are categorized into two groups: status flags and control flags. The status flags reflect the result of arithmetic and logical operations, while the control flags are used to control the operation of the processor.

The 16-bit register layout is as follows: bits 0, 2, 4, 6, 7, and 11 are status flags, while bits 8, 9, and 10 are control flags. Bits 1, 3, 5, 12, 13, 14, and 15 are undefined.

Status Flags:

• Carry Flag (CF): Set to 1 if there is an overflow out of the most significant bit (MSB) after an addition or a borrow after a subtraction.
• Parity Flag (PF): Set to 1 if the lower 8 bits of the result contain an even number of 1s.
• Auxiliary Carry Flag (AF): Set to 1 if there is a carry from bit 3 to bit 4 during an addition or a borrow from bit 4 to bit 3 during a subtraction.
• Zero Flag (ZF): Set to 1 if the result of an operation is zero.
• Sign Flag (SF): Set to 1 if the MSB of the result is 1, indicating a negative number.
• Overflow Flag (OF): Set to 1 if a signed arithmetic operation results in a value that exceeds the capacity of the destination register.

Control Flags:

• Trap Flag (TF): When set to 1, the processor enters single-step mode, allowing the execution of one instruction at a time for debugging.
• Interrupt Flag (IF): When set to 1, the processor recognizes external maskable interrupts. When 0, these interrupts are ignored.
• Direction Flag (DF): Used for string manipulation instructions. If 0, the string is processed from lower to higher memory addresses (auto-increment); if 1, it is processed from higher to lower addresses (auto-decrement).