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JNTU B.Tech II SWITCHING THEORY AND LOGIC DESIGN Previous Question Paper (May - 2019 - R16)

B.Tech | II | II | R16 | May - 2019

Answer PaperPaper Code: 134CFMaximum Marks: 75Time: 3 Hours

Note: This question paper contains two parts A and B. Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit. Each question carries 10 marks and may have a, b, c as sub questions.

Part A

125 marks
a

Perform the following conversions (476.64)10 = ( )2 = ( )8.

2 marks

Answer

(476.64)10 = (111011100.10100)2 = (734.50)8.

b

Perform the following operation using 2’s complement method 1111.10 – 0101.11.

3 marks

Answer

To perform 1111.10 - 0101.11, find the 2's complement of 0101.11, which is 1010.01. Adding this to 1111.10 gives 1111.10 + 1010.01 = 11001.11. Discarding the carry results in 1001.11.

c

Define Multiplexer. Explain in brief about 2:1 Mux.

2 marks

Answer

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d

Explain the procedure to construct the 3 variable K-map with an example.

3 marks

Answer

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e

Derive the characteristic equations of D and T flipflop.

2 marks

Answer

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f

Give the differences between latches and flipflops.

3 marks

Answer

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g

Define state diagram.

2 marks

Answer

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h

List the features of sequential circuits.

3 marks

Answer

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i

What are finite state machines?

2 marks

Answer

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j

List the limitations of finite state machines.

3 marks

Answer

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Part B

2

Design and realize the 3 bit binary to unit distance code using NOR gates.

10 marks

Answer

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OR
3

Simplify and realize the following Boolean expression using logic gates.

10 marks
a

Y=AB+A′C+BC

5 marks

Answer

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b

Y=(A+B′+C′)(A+B′+C)

5 marks

Answer

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4

Design a digital system to compare two binary numbers of 1 bit by using logic gates.

10 marks

Answer

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OR
5

Realize 3:8 maxterm generator using 2:4 maxterm generators. Using the same, Design a system to provide the difference of two numbers. Use external two input gates only.

10 marks

Answer

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6

Explain master slave JK flipflop with neat timing diagram.

10 marks

Answer

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OR
7

Explain the principle of Universal shift Register(USR). Using the same, design 4-bit, mod-8 twisted ring counter.

10 marks

Answer

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8

Design a digital system using data flipflops to monitor the status of the bookrack of maximum occupancy 10. The number of books available in the bookrack on a daily basis for the following conditions over a week.

  • On Monday, there were 10 books.
  • On Tuesday, 2 books were removed and donated to near by library.
  • On Wednesday, one book is added to the bookrack.
  • Next day, 3 books were removed from the rack and given it to neighbour.
  • On Friday, one book was taken out for reading.
  • On Saturday, neighbour returned only two books.
  • All the remaining books were taken out on Sunday to clean the rack.
10 marks

Answer

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OR
910 marks
a

Discuss about the approaches of designing synchronous sequential finite state machines.

5 marks

Answer

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b

Design a digital controller for the state table shown below using sequential component as single input data flip flop.

Present stateNext state, Output(z) (Input(x)=0)Next state, Output(z) (Input(x)=1)
AC,0B,1
BD,0D,0
CC,1A,0
DA,1A,0
5 marks

Answer

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10

Draw the state diagram of a Mealy machine that produces a 1 output if there have been four or more consecutive 1 inputs or two or more consecutive 0 inputs.

10 marks

Answer

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OR
1110 marks
a

With a neat block diagram, explain the moore model of a clocked synchronous sequential circuit.

5 marks

Answer

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b

Illustrate partition techniques in sequential circuits.

5 marks

Answer

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This page contains the question paper of SWITCHING THEORY AND LOGIC DESIGN from JNTU for B.Tech MECT-MCT-MEM II II, May - 2019, R16.

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