JNTU B.Tech III MICROPROCESSORS AND MICROCONTROLLERS Previous Question Paper (August - 2022 - R18)

An addressing mode is the method by which the 8086 microprocessor specifies the location of an operand in an instruction. The 8086 supports several addressing modes:

• Immediate Addressing: The operand is specified directly in the instruction (e.g., MOV AX, 1234H).
• Register Addressing: The operand is held in a register (e.g., MOV AX, BX).
• Direct Addressing: The memory address of the operand is given directly in the instruction (e.g., MOV AX, [1234H]).
• Register Indirect Addressing: The address of the operand is stored in a base or index register (BX, BP, SI, or DI) (e.g., MOV AX, [BX]).
• Based Addressing: The effective address is the sum of a base register (BX or BP) and an 8-bit or 16-bit displacement (e.g., MOV AX, [BX+05H]).
• Indexed Addressing: The effective address is the sum of an index register (SI or DI) and a displacement (e.g., MOV AX, [SI+05H]).
• Based-Indexed Addressing: The effective address is the sum of a base register, an index register, and an optional displacement (e.g., MOV AX, [BX+SI+05H]).
• Relative Addressing: Used in branch instructions; the target address is the sum of the current instruction pointer and a signed 8-bit displacement.

The 8086 architecture is divided into two independent functional units: the Bus Interface Unit (BIU) and the Execution Unit (EU).

• Bus Interface Unit (BIU): Responsible for all external bus operations. It contains the Segment Registers (CS, DS, SS, ES), Instruction Pointer (IP), and an Instruction Queue. It fetches instructions from memory, reads/writes data, and calculates physical addresses using the adder.
• Execution Unit (EU): Responsible for decoding and executing instructions. It contains the Arithmetic Logic Unit (ALU), General Purpose Registers (AX, BX, CX, DX), Pointer/Index Registers (SP, BP, SI, DI), and the Flag Register. It receives instructions from the BIU queue, processes them, and updates the flags based on results.

The Instruction Queue allows the BIU to prefetch up to 6 bytes of instructions while the EU is busy executing, a process known as pipelining, which significantly increases processor throughput.