JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

Course Objectives

The objectives of the course are to:

• 1. Give exposure to different steps involved in the fabrication of ICs using MOS transistor, CMOS/BICMOS transistors, and passive components.
• 2. Explain electrical properties of MOS and BiCMOS devices to analyze the behavior of inverters designed with various loads.
• 3. Give exposure to the design rules to be followed to draw the layout of any logic circuit.
• 4. Provide concept to design different types of logic gates using CMOS inverter and analyze their transfer characteristics.
• 5. Provide design concepts to design building blocks of data path of any system using gates.
• 6. Understand basic programmable logic devices and testing of CMOS circuits.

Course Outcomes

Upon successfully completing the course, the student should be able to:

• 1. Acquire qualitative knowledge about the fabrication process of integrated circuit using MOS transistors.
• 2. Choose an appropriate inverter depending on specifications required for a circuit
• 3. Draw the layout of any logic circuit which helps to understand and estimate parasitic of any logic circuit
• 4. Design different types of logic gates using CMOS inverter and analyze their transfer characteristics
• 5. Provide design concepts required to design building blocks of data path using gates.
• 6. Design simple memories using MOS transistors and can understand design of large memories.
• 7. Design simple logic circuit using PLA, PAL, FPGA and CPLD.
• 8. Understand different types of faults that can occur in a system and learn the concept of testing and adding extra hardware to improve testability of system

UNIT - I

Introduction: Introduction to IC Technology – MOS, PMOS, NMOS, CMOS & BiCMOS Basic Electrical Properties: Basic Electrical Properties of MOS and BiCMOS Circuits: Ids- Vds relationships, MOS transistor threshold Voltage, gm, gds, Figure of merit ωo; Pass transistor, NMOS Inverter, Various pull ups, CMOS Inverter analysis and design, Bi-CMOS Inverters.

UNIT - II

VLSI Circuit Design Processes: VLSI Design Flow, MOS Layers, Stick Diagrams, Design Rules and Layout, 2 µm CMOS Design rules for wires, Contacts and Transistors Layout Diagrams for NMOS and CMOS Inverters and Gates, Scaling of MOS circuits.

R16 B.TECH BIOMEDICAL ENGG.

UNIT - III

Gate Level Design: Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Time delays, Driving large capacitive loads, Wiring capacitance, Fan – in, Fan – out, Choice of layers.

UNIT - IV

Data Path Subsystems: Subsystem Design, Shifters, Adders, ALUs, Multipliers, Parity generators, Comparators, Zero/One Detectors, Counters. Array Subsystems: SRAM, DRAM, ROM, Serial Access Memories.

UNIT - V

Programmable Logic Devices: PLAs, FPGAs, CPLDs, Standard Cells, Programmable Array Logic, Design Approach, Parameters influencing low power design. CMOS Testing: CMOS Testing, Need for testing, Test Principles, Design Strategies for test, Chip level Test Techniques.

TEXT BOOKS:

• 1. Essentials of VLSI circuits and systems – Kamran Eshraghian, Eshraghian Dougles and A. Pucknell, PHI, 2005 Edition
• 2. CMOS VLSI Design – A Circuits and Systems Perspective, Neil H. E Weste, David Harris, Ayan Banerjee, 3rd Ed, Pearson, 2009.

REFERENCE BOOKS:

• 1. CMOS logic circuit Design - John .P. Uyemura, Springer, 2007.
• 2. Modern VLSI Design - Wayne Wolf, Pearson Education, 3rd Edition, 1997. R16 B.TECH BIOMEDICAL ENGG.