JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

EC703PC: VLSI & E-CAD LAB

B.Tech IV Year I Semester (R16)

List of Experiments

Design and implementation of the following CMOS digital/analog circuits using Cadence / Mentor Graphics / Synopsys /Equivalent CAD tools. The design shall include Gate-level design, Transistor-level design, Hierarchical design, Verilog HDL/VHDL design, Logic synthesis, Simulation and verification, Scaling of CMOS Inverter for different technologies, study of secondary effects ( temperature, power supply and process corners), Circuit optimization with respect to area, performance and/or power, Layout, Extraction of parasitics and back annotation, modifications in circuit parameters and layout consumption, DC/transient analysis, Verification of layouts (DRC, LVS)

E-CAD programs: Programming can be done using any complier. Down load the programs on FPGA/CPLD boards and performance testing may be done using pattern generator (32 channels) and logic analyzer apart from verification by simulation with any of the front end tools.

  • 1. HDL code to realize all the logic gates
  • 2. Design of 2-to-4 decoder
  • 3. Design of 8-to-3 encoder (without and with priority)
  • 4. Design of 8-to-1 multiplexer and 1-to-8 demultiplexer
  • 5. Design of 4 bit binary to gray code converter
  • 6. Design of 4 bit comparator
  • 7. Design of Full adder using 3 modeling styles
  • 8. Design of flip flops: SR, D, JK, T
  • 9. Design of 4-bit binary, BCD counters ( synchronous/ asynchronous reset) or any sequence counter
  • 10. Finite State Machine Design VLSI programs:
  • Introduction to layout design rules. Layout, physical verification, placement & route for complex design, static timing analysis, IR drop analysis and crosstalk analysis of the following:
  • 1. Basic logic gates
  • 2. CMOS inverter
  • 3. CMOS NOR/ NAND gates
  • 4. CMOS XOR and MUX gates
  • 5. Static / Dynamic logic circuit (register cell)
  • 6. Latch
  • 7. Pass transistor
  • 8. Layout of any combinational circuit (complex CMOS logic gate).
  • 9. Analog Circuit simulation (AC analysis) – CS & CD amplifier

Note

Any SIX of the above experiments from each part are to be conducted (Total 12)

R16 B.TECH ECE.

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