JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

Prerequisite

Switching Theory & Logic Design

UNIT - I

Simple Programmable Logic Devices (SPLDS): Programmable Read Only Memories (PROMs), Programmable Logic Arrays (PLAs), Programmable Array Logic (PALs), the Masked Gate Array ASIC. Complex Programmable Logic Devices (CPLDs): CPLD Architectures, Function Blocks, I/O Blocks, Clock Drivers, Interconnect CPLD Technology and Programmable Elements, Embedded Devices. Field Programmable Gate Arrays (FPGAs): FPGA Architectures, Configurable Logic Blocks, Configurable I/o Blocks, Embedded Devices, Programmable Inter Connect, Clock Circuitry, SRAM vs. Anti-fuse programming, FPGA Selection Criteria.

UNIT - II

Universal Design Methodology for Programmable Devices: Introduction to UDM and UDM-PD, writing a Specification, Specification Review, Choosing Device and Tools, Design, Verification, Final Review, System Integration and Test. Hardware Descriptive Languages, Structure of VHDL & Verilog module, operator, Data types, Top-Down Design, Synchronous Design, Floating Nodes, Bus Contention, One-Hot state Encoding.

UNIT - III

Data flow Description and Behavioral Descriptions: Introduction to styles types of hardware description –Behavioral, Structural, Dataflow and Mixed type and language descriptions. Data flow Description: Structure of the dataflow description, Signal Declaration and Assignment Statements, Concurrent Signal assignments, Constant declaration and assignments, assigning a delay time to the signal, Data type-Vectors. Behavioral Descriptions: Structure of the HDL Behavioral description, The VHDL/ Verilog HDL variable – assignment statement, sequential statement – IF, signal and variable assignment, CASE & LOOP statements

UNIT - IV

Structural and Switch level Descriptions. Structural Description: Organization of the structural description, binding, state machines, Generate (HDL), Generic (VHDL), and parameter (Verilog).

R16 B.TECH ECE.

Switch level Description: Useful definitions, Single NMOS & PMOS switches-verilog & VHDL description of NMOS & PMOS Switches, serial and parallel combinations of switches, Switch level Description of –primitive gates, Simple combinational logics, simple sequential circuits, Bidirectional Switches.

UNIT - V

Procedures, Tasks, Functions and Verification: Mixed type descriptions, Procedures and Tasks: Procedures (VHDL), Tasks (Verilog), Examples of Procedures and Tasks, Functions in VHDL & Verilog HDL. Verification: Introduction to verification, simulation, static timing Analysis, Association languages and formal verification.

TEXT BOOKS:

• 1. Designing with FPGAS & CPLDS- Bob Zeidman, CMP Books, First Printed in India 2011
• 2. HDL Programming Fundamental-VHDL & Verilog, Botros, Cengage Learning, Third Indian Reprint 2012 R16 B.TECH ECE.