JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

Prerequisite

Switching Theory and Logic Design

UNIT - I

Integrated Design Process and Methodology, Hardware Descriptive language and digital circuit primitives- Flip flop, latch, Three state Buffer, combinational gates, HDL Synthesis Rules, pads. HDL Simulation Environment, Synthesis Environment, synthesis Technology library, HDL Design process for a Block.

UNIT - II

Design of Basic Combinational circuits through VHDL/Verilog HDL Selectors, Encoder, Code Converter, Equality Checker, Comparators, Half adder, Full adder, Carry ripple adder, carry look ahead adder, Count one circuit, leading zero Circuit, Barrel Shifter.

UNIT - III

Design of Basic Sequential Circuit Through VHDL/Verilog HDL Signal manipulator, counter, Shift Register, Parallel to serial Converter, Serial to parallel convertor, General framework to design registers- Interrupt Registers, DMA and control Register, configuration registers, Register Block portioning and synthesis.

UNIT - IV

Clock and Reset Circuits Clock Buffer and Clock Tree, Clock Tree generation, Reset Circuitry, Clock Skew and Fixes, Synchronization between clock domains, clock Divider, Gated clock.

UNIT - V

Design Case Study Design Description, Design partition, Design verification, Design Synthesis, Worst-case Timing analysis, Best-case Timing Analysis, Net list Generation, Post layout Verification, Design Management.

TEXT BOOK:

• 1. Digital Systems Design with VHDL and Synthesis – K. C. Chang, Wiley-India Edition R16 B.TECH ECE.