JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

Note

Any SIX of the following experiments from each part are to be conducted (Total 12)

Part - I All the following experiments have to be implemented using HDL

• 1. Realize all the logic gates
• 2. Design of 8-to-3 encoder (without and with priority) and 2-to-4 decoder
• 3. Design of 8-to-1 multiplexer and 1-to-8 demultiplexer
• 4. Design of 4 bit binary to gray code converter
• 5. Design of 4 bit comparator
• 6. Design of Full adder using 3 modeling styles
• 7. Design of flip flops: SR, D, JK, T
• 8. Design of 4-bit binary, BCD counters (synchronous/ asynchronous reset) or any sequence counter
• 9. Finite State Machine Design Part-II Layout, physical verification, placement & route for complex design, static timing analysis, IR drop analysis and crosstalk analysis for the following:
• 1. Basic logic gates
• 2. CMOS inverter
• 3. CMOS NOR/ NAND gates
• 4. CMOS XOR and MUX gates
• 5. Static / Dynamic logic circuit (register cell)
• 6. Latch
• 7. Pass transistor
• 8. Layout of any combinational circuit (complex CMOS logic gate). R18 B.TECH ECE III YEAR