JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

Prerequisite

Digital Electronics

Course Objectives:

• To understand basic components of computers.
• To understand the architecture of 8086 processor.
• To understand the instruction sets, instruction formats and various addressing modes of 8086.
• To understand the representation of data at the machine level and how computations are performed at machine level.
• To understand the memory organization and I/O organization.
• To understand the parallelism both in terms of single and multiple processors.

Course Outcomes

At the end of this course, students will demonstrate the ability to

• Understand the concepts of microprocessors, their principles and practices.
• Write efficient programs in assembly language of the 8086 family of microprocessors.
• Organize a modern computer system and be able to relate it to real examples.
• Develop the programs in assembly language for 80286, 80386 and MIPS processors in real and protected modes.
• Implement embedded applications using ATOM processor.

UNIT - I

Introduction to Computer Organization Architecture and function of general computer system, CISC Vs RISC, Data types, Integer Arithmetic - Multiplication, Division, Fixed and Floating-point representation and arithmetic, Control unit operation, Hardware implementation of CPU with Micro instruction, microprogramming, System buses, Multi-bus organization.

UNIT - II

Memory Organization System memory, Cache memory - types and organization, Virtual memory and its implementation, Memory management unit, Magnetic Hard disks, Optical Disks. Input – Output Organization Accessing I/O devices, Direct Memory Access and DMA controller, Interrupts and Interrupt Controllers, Arbitration, Multilevel Bus Architecture, Interface circuits - Parallel and serial port. Features of PCI and PCI Express bus.

UNIT - III

16 AND 32 Microprocessors 80x86 Architecture, IA – 32 and IA – 64, Programming model, Concurrent operation of EU and BIU, Real mode addressing, Segmentation, addressing modes of 80x86, Instruction set of 80x86, I/O addressing in 80x86

UNIT - IV

Pipelining Introduction to pipelining, Instruction level pipelining (ILP), compiler techniques for ILP,Data hazards, Dynamic scheduling, Dependability, Branch cost, Branch Prediction, Influence on instruction set.

R18 B.TECH EEE III YEAR

UNIT - V

Different Architectures VLIW Architecture, DSP Architecture, SoC architecture, MIPS Processor and programming

TEXT BOOKS:

• 1. V. Carl, G. Zvonko and S. G. Zaky, “Computer organization”, McGraw Hill, 1978.
• 2. B. Brey and C. R. Sarma, “The Intel microprocessors”, Pearson Education, 2000.

REFERENCES:

• 1. J. L. Hennessy and D. A. Patterson, “Computer Architecture A Quantitative Approach”, Morgan Kauffman, 2011.
• 2. W. Stallings, “Computer organization”, PHI, 1987.
• 3. P. Barry and P. Crowley, “Modern Embedded Computing”, Morgan Kaufmann, 2012.
• 4. N. Mathivanan, “Microprocessors, PC Hardware and Interfacing”, Prentice Hall, 2004.
• 5. Y. C. Lieu and G. A. Gibson, “Microcomputer Systems: The 8086/8088 Family”, Prentice Hall India, 1986.
• 6. J. Uffenbeck, “The 8086/8088 Design, Programming, Interfacing”, Prentice Hall, 1987.
• 7. B. Govindarajalu, “IBM PC and Clones”, Tata McGraw Hill, 1991.
• 8. P. Able, “8086 Assembly Language Programming”, Prentice Hall India. R18 B.TECH EEE III YEAR