JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
DIGITAL LOGIC DESIGN LABORATORY
B.Tech II Year I Semester (R22)
Course Outcomes
Upon completing this course, the students will be able to
1. Acquire the knowledge on numerical information in different forms and Boolean Algebra theorems.
2. Define Postulates of Boolean algebra and to minimize combinational functions, and design the combinational circuits.
3. Design and analyze sequential circuits for various cyclic functions.
4. Characterize logic families and analyze them for the purpose of AC and DC parameters. Course PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 CO1 3 2 3 1 2 1 - - 1 - - 2 CO2 3 2 2 1 2 1 - - 1 - - 2 CO3 2 3 3 2 2 1 - - 1 - - 1 CO4 3 2 1 1 1 - - - - - - -
List of Experiments
1. Realization of Logic circuit to generate r’s Compliment using Logic Gates.
2. Realization of given Boolean function using universal gates and minimizing the same.Compare the gate count before and after minimization.
3. Design and realize Full Adder circuit using gates/universal gates. Implement Full Subtractor using full adder.
4. Designing a 2 – bit Comparator using AND, OR and NOT gates. Realize 4 – bit Comparator using 2 – bit Comparators.
5. Realize 2:1 MUX using the given gates and Design 8:1 using 2:1 MUX.
6. Implement the given Boolean function using the given MUX(ex: code converters).
7. Realize a 2x4 Decoder using logic gates and implement 3x8 Decoder using 2x4 Decoder.
8. Implement the given Boolean function using given Decoders.
9. Convert Demultiplexer to Decoder and vise versa.
10. Verification of truth tables of flipflops using different clocks (level triggering, positive and negative edge triggering) also converts the given flipflop from one type to other.
11. Designing of Universal n-bit shift register using flipflops and Multiplexers. Draw the timing diagram of the Shift Register.
12. Design a Synchronous binary counter using D-flipflop/given flipflop.
13. Design a asynchronous counter for the given sequence using given flipflops.
14. Designing of MOD 8 Counter using JK flipflops.
15. Designing of sequence detecting State Machine with minimal states using the given flipflops.
16. Designing of Parity Bit(even/odd) generator using the given flipflops.
17. Realize all logic gates with TTL logic.
18. Realize all logic gates with DTL logic. *Design a sequence detector to detect a given sequence and verify practically *Design a serial subtractor for 4 bit binary numbers Major Equipment required for Laboratories:
1. 5 V Fixed Regulated Power Supply/ 0-5V or more Regulated Power Supply.