JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

ADHOC WIRELESS SENSOR NETWORKS

M.Tech I Year I Semester (R17)

UNIT - I

Wireless Local Area Networks: Introduction, wireless LAN Topologies, Wireless LAN Requirements, Physical Layer- Infrared Physical Layer, Microwave based Physical Layer Alternatives, Medium Access Control Layer- HIPERLAN 1 Sublayer, IEEE 802.11 MAC Sublayer and Latest Developments- 802.11a, 802.11b, 802.11g Personal Area Networks: Introduction to PAN technology and Applications, Bluetooth - specifications, Radio Channel, Piconets and Scatternets, Inquiry, Paging and Link Establishment, Packet Format, Link Types, Power Management, Security, Home RF -Physical and MAC Layer

UNIT - II

Ad-Hoc Wireless Networks: Introduction; Cellular and Ad-Hoc Wireless Networks; Issues in Ad-Hoc Wireless Networks: Medium Access Scheme, Routing, Multicasting, Transport Layer Protocols, Quality of Service Provisioning, Energy Management, Scalability

UNIT - III

Medium Access Control Protocols: Introduction; Issues in Designing a MAC protocol: Bandwidth efficiency, Quality of Service support, Synchronization, Hidden and exposed terminal problems, Error prone shared broadcast channel, mobility nodes; Design goals of a MAC protocol; Classification of MAC protocols; Contention-based protocols: MACAW, Floor acquisition multiple access protocol, Busy tone multiple access protocols, MACA by invitation, Media access with reduced handshake; Contention-based protocols with reservation mechanisms; Contention-based MAC protocols with scheduling mechanisms; MAC protocols that use directional antennas

UNIT - IV

Routing and Transport Layer Protocols: Introduction, issues in designing a routing protocol, Classification of routing protocols, Table-driven protocols, On-demand routing protocols, Hybrid routing protocols, Routing with efficient flooding mechanisms, Hierarchical routing protocols, Power- aware routing protocols; Introduction to transport layer protocols, design issues and goals of transport layer protocol, Classification of transport layer solutions

UNIT - V

Wireless Sensor Networks: Introduction, Sensor Network Architecture, Data Dissemination, Data gathering, MAC protocols for Sensor Networks, Location Discovery, Quality of a Sensor Network

TEXT BOOKS:

  • 1. C. Siva Ram Murthy, “Ad Hoc Wireless Networks”, 2004, Pearson Education.
  • 2. P Nicopolitidis and M S Obaidat, “Wireless Networks”, Wiley India Edition 2003.

REFERENCE BOOKS:

st

  • 1. C.K. Toh, “Ad-Hoc Mobile Wireless Networks: Protocols and Systems”, 1 Edition, Pearson Education.
  • 2. Carlos de Morais Cordeiro and Dharma Prakash Agrawal, “Ad Hoc and Sensor Networks”, 2011, World Scientific.
  • 3. Kazen Sohraby, Daniel Minoli, Taieb Znati, “Wireless Sensor Networks”, 1991, Wiley Student Edition
  • 4. C.S. Raghavendra, Krishna M. SivaLingam, “Wireless Sensor Networks”, 2004, Springer.
  • 5. Jagannathan Sarangapani, “Wireless Ad- hoc and Sensor Networks: Protocols, Performance and Control”, CRC Press M. TECH. I YEAR I SEMESTER ELECTRONICS AND COMMUNICATION ENGINEERING DIGITAL SYSTEM DESIGN LAB Part –I Programming can be done using any complier. Down load the programs on FPGA/CPLD boards and performance testing may be done using pattern generator (32 channels) and logic analyzer apart from verification by simulation with any of the front end tools.
  • 1. HDL code to realize all the logic gates
  • 2. Design and Simulation of adder, Serial Binary Adder, Multi Precession Adder, Carry
  • 3. Look Ahead Adder.
  • 4. Design of 2-to-4 decoder
  • 5. Design of 8-to-3 encoder (without and with parity)
  • 6. Design of 8-to-1 multiplexer
  • 7. Design of 4 bit binary to gray converter
  • 8. Design of Multiplexer/ Demultiplexer, comparator
  • 9. Design of Full adder using 3 modeling styles
  • 10. Design of flip flops: SR, D, JK, T
  • 11. Design of 4-bit binary, BCD counters ( synchronous/ asynchronous reset) or any sequence counter
  • 12. Design of a N- bit Register of Serial- in Serial –out, Serial in parallel out, Parallel in
  • 13. Serial out and Parallel in Parallel Out.
  • 14. Design of Sequence Detector (Finite State Machine- Mealy and Moore Machines).
  • 15. Design of 4- Bit Multiplier, Divider.
  • 16. Design of ALU to Perform – ADD, SUB, AND-OR, 1’s and 2’s Compliment,
  • 17. Multiplication and Division.
  • 18. Design of Finite State Machine.
  • 19. Implementing the above designs on Xilinx/Altera/Cypress/equivalent based FPGA/CPLD kits . Part –II
  • 1. Static and Dynamic Characteristics of CMOS Inverter
  • 2. Implementation of EX-OR gate using complementary CMOS, Psuedo-NMOS, Dynamic and domino logic style
  • 3. Implementation of Full Adder using Transmission Gates

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