JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

UNIT - I

Fundamentals of Computer Design: Fundamentals of Computer design, Changing faces of computing and task of computer designer, Technology trends, Cost price and their trends, measuring and reporting performance, quantitative principles of computer design, Amdahl’s law. Instruction set principles and examples- Introduction, classifying instruction set- memory addressing- type and size of operands, operations in the instruction set.

UNIT - II

Pipelines: Introduction ,basic RISC instruction set ,Simple implementation of RISC instruction set, Classic five stage pipe line for RISC processor, Basic performance issues in pipelining , Pipeline hazards, Reducing pipeline branch penalties. Memory Hierarchy Design: Introduction, review of ABC of cache, Cache performance , Reducing cache miss penalty, Virtual memory.

UNIT - III

Instruction Level Parallelism the Hardware Approach: Instruction-Level parallelism, Dynamic scheduling, Dynamic scheduling using Tomasulo’s approach, Branch prediction, high performance instruction delivery- hardware based speculation. ILP Software Approach: Basic compiler level techniques, static branch prediction, VLIW approach, Exploiting ILP, Parallelism at compile time, Cross cutting issues -Hardware verses Software.

UNIT - IV

Multi Processors and Thread Level Parallelism: Multi Processors and Thread level Parallelism- Introduction, Characteristics of application domain, Systematic shared memory architecture, Distributed shared – memory architecture, Synchronization.

UNIT - V

Inter Connection and Networks: Introduction, Interconnection network media, Practical issues in interconnecting networks, Examples of inter connection, Cluster, Designing of clusters. Intel Architecture: Intel IA- 64 ILP in embedded and mobile markets Fallacies and pit falls

TEXT BOOKS:

• 1. John L. Hennessy, David A. Patterson, “Computer Architecture: A Quantitative Approach”, 3rd Edition, An Imprint of Elsevier.

REFERENCE BOOKS:

• 1. John P. Shen and Miikko H. Lipasti, “Modern Processor Design : Fundamentals of Super Scalar Processors”,
• 2. Kai Hwang, Faye A.Brigs., “Computer Architecture and Parallel Processing”, McGraw Hill.,
• 3. DezsoSima, Terence Fountain, Peter Kacsuk , “Advanced Computer Architecture - A Design Space Approach”, Pearson Education. M. TECH. – I YEAR – I SEMESTER VLSI/ VLSI DESIGN/VLSI SYSTEM DESIGN DIGITAL IC DESIGN LAB Part –I Programming can be done using any complier. Down load the programs on FPGA/CPLD boards and performance testing may be done using pattern generator (32 channels) and logic analyzer apart from verification by simulation with any of the front end tools.
• 1. HDL code to realize all the logic gates
• 2. Design and Simulation of adder, Serial Binary Adder, Multi Precession Adder, Carry
• 3. Look Ahead Adder.
• 4. Design of 2-to-4 decoder
• 5. Design of 8-to-3 encoder (without and with parity)
• 6. Design of 8-to-1 multiplexer
• 7. Design of 4 bit binary to gray converter
• 8. Design of Multiplexer/ Demultiplexer, comparator
• 9. Design of Full adder using 3 modeling styles
• 10. Design of flip flops: SR, D, JK, T
• 11. Design of 4-bit binary, BCD counters ( synchronous/ asynchronous reset) or any sequence counter
• 12. Design of a N- bit Register of Serial- in Serial –out, Serial in parallel out, Parallel in
• 13. Serial out and Parallel in Parallel Out.
• 14. Design of Sequence Detector (Finite State Machine- Mealy and Moore Machines).
• 15. Design of 4- Bit Multiplier, Divider.
• 16. Design of ALU to Perform – ADD, SUB, AND-OR, 1’s and 2’s Compliment,
• 17. Multiplication, and Division.
• 18. Design of Finite State Machine.
• 19. Implementing the above designs on Xilinx/Altera/Cypress/equivalent based FPGA/CPLD kits Part –II
• 1. Static and Dynamic Characteristics of CMOS Inverter
• 2. Implementation of EX-OR gate using complementary CMOS, Psedo-NMOS, Dynamic and domino logic style
• 3. Implementation of Full Adder using Transmission Gates