JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

UNIT - I

PRELIMINARIES: Introduction to Design Methodologies, Design Automation tools, Algorithmic Graph Theory, Computational complexity, Tractable and Intractable problems.

UNIT - II

GENERAL PURPOSE METHODS FOR COMBINATIONAL OPTIMIZATION: Backtracking, Branch and Bound, Dynamic Programming, Integer Linear Programming, Local Search, Simulated Annealing, Tabu search, Genetic Algorithms.

UNIT - III

LAYOUT COMPACTION, PLACEMENT, FLOOR PLANNING AND ROUTING: Problems, Concepts and Algorithms. MODELLING AND SIMULATION: Gate Level Modelling and Simulation, Switch level Modelling and Simulation.

UNIT - IV

LOGIC SYNTHESIS AND VERIFICATION: Basic issues and Terminology, Binary-Decision diagrams, Two-Level logic Synthesis. HIGH-LEVEL SYNTHESIS: Hardware Models, Internal representation of the input Algorithm, Allocation, Assignment and Scheduling, Some Scheduling Algorithms, Some aspects of Assignment problem, High-level Transformations.

UNIT - V

PHYSICAL DESIGN AUTOMATION OF FPGAs: FPGA technologies, Physical Design cycle for FPGAs, partitioning and Routing for segmented and staggered Models. PHYSICAL DESIGN AUTOMATION OF MCMs : MCM technologies, MCM physical design cycle, Partitioning, Placement - Chip Array based and Full Custom Approaches, Routing – Maze routing, Multiple stage routing, Topologic routing, Integrated Pin – Distribution and routing, Routing and Programmable MCMs.

TEXT BOOKS:

• 1. S.H. Gerez, “Algorithms for VLSI Design Automation”, 1999, WILEY Student Edition, John Wiley & Sons (Asia) Pvt. Ltd.
• 2. Naveed Sherwani, “Algorithms for VLSI Physical Design Automation”, 3rd Edition, 2005, Springer International Edition.

REFERENCE BOOKS:

• 1. Hill & Peterson, “Computer Aided Logical Design with Emphasis on VLSI”, 1993, Wiley.
• 2. Wayne Wolf, “Modern VLSI Design: Systems on silicon”, 2nd ed., 1998, Pearson Education Asia.