JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

UNIT - I

MOS Transistor: Introduction, Ideal I-V Characteristics, C-V Characteristics, Non ideal I-V Effects, DC Transfer Characteristics. CMOS Process Technology: CMOS Technologies, Layout Design Rules, CMOS Process Enhancements, Technology related CAD Issues.

UNIT - II

Circuit Characterization: Delay Estimation, Logical effort and Transistor Sizing, Power Dissipation, Interconnect, Design Margin, Reliability, Scaling.

UNIT - III

Combinational and Sequential Circuit Design: Circuit Families, More circuit families, Low power Logic Design, Comparison of Circuit Families, Sequencing Static Circuits, Circuit Design of Latches and Flip-Flops, Static Sequencing Element Methodology, Sequencing Dynamic Circuits, Synchronizers.

UNIT - IV

Datapath Subsystems: Addition, Subtraction, Comparators, Counters, Boolean Logical Operations, Coding, Shifters, Multiplication, Division. Array Subsystems: SRAM, DRAM, Read-only Memory, Serial Access Memories, Content addressable Memory, PLAs, Array Yield, Reliability and Self-Test.

UNIT - V

Design Methodology and Tools: Design Methodology, Design Flows, Design Economics, Data Sheets and Documentation, CMOS Physical Design Styles, Interchange Formats. Special Purpose Subsystem: Packaging.

TEXTBOOKS:

• 1. Neil Weste, David Harris, Ayan Banerjee, “CMOS VLSI DESIGN”, 3rd Edition, Pearson.