JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

UNIT - I

Introduction to Programmable Logic Devices:Introduction, Simple Programmable Logic Devices – Read Only Memories, Programmable Logic Arrays, Programmable Array Logic, Programmable Logic Devices/Generic Array Logic; Complex Programmable Logic Devices – Architecture of Xilinx Cool Runner XCR3064XL CPLD, CPLD Implementation of a Parallel Adder with Accumulation.

UNIT - II

Field Programmable Gate Arrays: Organization of FPGAs, FPGA Programming Technologies, Programmable Logic Block Architectures, Programmable Interconnects, Programmable I/O blocks in FPGAs, Dedicated Specialized Components of FPGAs, Applications of FPGAs.

UNIT - III

SRAM Programmable FPGAs: Introduction, Programming Technology, Device Architecture, The Xilinx XC2000, XC3000 and XC4000 Architectures.

UNIT - IV

Anti-Fuse Programmed FPGAs: Introduction, Programming Technology, Device Architecture, The Actel ACT1, ACT2 and ACT3 Architectures.

UNIT - V

Design Applications: General Design Issues, Counter Examples, A Fast Video Controller, A Position Tracker for a Robot Manipulator, A Fast DMA Controller, Designing Counters with ACT devices, Designing Adders and Accumulators with the ACT Architecture.

TEXT BOOKS:

• 1. Stephen M. Trimberger, “Field Programmable Gate Array Technology”, Springer International Edition.
• 2. Charles H. Roth Jr, Lizy Kurian John, “Digital Systems Design”, Cengage Learning.

REFERENCE BOOKS:

• 1. John V. Oldfield, Richard C. Dorf, “Field Programmable Gate Arrays”, Wiley India.
• 2. Pak K. Chan/Samiha Mourad, “Digital Design Using Field Programmable Gate Arrays”, Pearson Low Price Edition.
• 3. Ian Grout, “Digital Systems Design with FPGAs and CPLDs”, Elsevier, Newnes.
• 4. Wayne Wolf, “FPGA based System Design”, Prentice Hall Modern Semiconductor Design Series. M. TECH. I YEAR I SEMESTER EMBEDDED SYSTEMS & VLSI DESIGN/VLSI AND EMBEDDED SYSTEMS/ ELECTRONICS DESIGN TECHNOLOGY. VLSI LAB

Note:

• Minimum of 10 programs from Part –I and 2 programs from Part -II are to be conducted. Design and implementation of the following CMOS digital/analog circuits must be carried out using Cadence / Mentor Graphics / Synopsys / Equivalent CAD tools. The design shall include Gate- level design, Transistor-level design, Hierarchical design, Verilog HDL/VHDL design, Logic synthesis, Simulation and verification. Part –I: VLSI Front End Design programs: Programming can be done using any complier. Down load the programs on FPGA/CPLD boards and performance testing may be done using pattern generator (32 channels) and logic analyzer apart from verification by simulation with any of the front end tools.
• 1. HDL code to realize all the logic gates
• 2. Design and Simulation of adder, Serial Binary Adder, Multi Precession Adder, Carry
• 3. Look Ahead Adder.
• 4. Design of 2-to-4 decoder
• 5. Design of 8-to-3 encoder (without and with parity)
• 6. Design of 8-to-1 multiplexer
• 7. Design of 4 bit binary to gray converter
• 8. Design of Multiplexer/ Demultiplexer, comparator
• 9. Design of Full adder using 3 modeling styles
• 10. Design of flip flops: SR, D, JK, T
• 11. Design of 4-bit binary, BCD counters ( synchronous/ asynchronous reset) or any sequence counter
• 12. Design of a N- bit Register of Serial- in Serial –out, Serial in parallel out, Parallel in
• 13. Serial out and Parallel in Parallel Out.
• 14. Design of Sequence Detector (Finite State Machine- Mealy and Moore Machines).
• 15. Design of 4- Bit Multiplier, Divider.
• 16. Design of ALU to Perform – ADD, SUB, AND-OR, 1’s and 2’s Compliment, Multiplication and Division.
• 17. Design of Finite State Machine.
• 18. Implementing the above designs on Xilinx/Altera/Cypress/equivalent based FPGA/CPLD kits. Part –II: VLSI Back End Design programs: Design and implementation of the following CMOS digital/analog circuits using Cadence / Mentor Graphics / Synopsys / Equivalent CAD tools. The design shall include Gate-level design/Transistor- level design/Hierarchical design/Verilog HDL or VHDL design, Logic synthesis, Simulation and verification, Scaling of CMOS Inverter for different technologies, study of secondary effects (temperature, power supply and process corners), Circuit optimization with respect to area, performance and/or power, Layout, Extraction of parasitic and back annotation, modifications in circuit parameters and layout consumption, DC/transient analysis, Verification of layouts (DRC, LVS).
• 1. Introduction to layout design rules
• 2. Layout, physical verification, placement & route for complex design, static timing analysis, IR drop analysis and crosstalk analysis of the following:
• Basic logic gates
• CMOS inverter
• CMOS NOR/ NAND gates
• CMOS XOR and MUX gates
• CMOS 1-bit full adder
• Static / Dynamic logic circuit (register cell)
• Latch
• Pass transistor
• 3. Layout of any combinational circuit (complex CMOS logic gate)- Learning about data paths