JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

Overview

EFFECTIVE FROM ACADEMIC YEAR 2017- 18 ADMITTED BATCH

COURSE STRUCTURE AND SYLLABUS

I Semester

Category Course Title Int. marks Ext. marks L T P C PC-1 Embedded System Design 25 75 4 0 0 4 PC-2 VLSI Technology 25 75 4 0 0 4 PC-3 CMOS Analog Integrated Circuit Design 25 75 4 0 0 4 PE-1 Hardware Software Co-Design 25 75 3 0 0 3 Digital System Design Advanced Computer Architecture PE-2 VLSI DSP Architectures 25 75 3 0 0 3 CMOS Digital Integrated Circuit Design CPLD and FPGA Architectures and Applications OE-1 *Open Elective – I 25 75 3 0 0 3 Laboratory I VLSI Laboratory 25 75 0 0 3 2 Seminar I Seminar 100 0 0 0 3 2 Total 275 525 21 0 6 25

II Semester

Category Course Title Int. marks Ext. marks L T P C PC-4 Low Power VLSI Design 25 75 4 0 1 4 PC-5 CMOS Mixed Signal Circuit Design 25 75 4 0 1 4 PC-6 Real Time Operating Systems 25 75 4 0 1 4 PE-3 Advanced Digital Signal Processing 25 75 3 0 0 3 System On Chip Architecture Embedded Networking PE4 Design for Testability 25 75 3 0 0 3 Physical Design Automation Scripting Languages OE-2 *Open Elective – II 25 75 3 0 0 3 Laboratory II Embedded Systems Laboratory 25 75 0 0 3 2 Seminar II Seminar 100 0 0 0 3 2 Total 275 525 21 0 6 25

III Semester

Course Title Int. Ext. L T P C marks marks Technical Paper Writing 100 0 0 3 0 2 Comprehensive Viva-Voce 0 100 0 0 0 4 Project work Review I 100 0 0 0 22 8 Total 200 100 0 3 22 14

IV Semester

Course Title Int. Ext. L T P C marks marks Project work Review II 100 0 0 0 24 8 Project Evaluation (Viva-Voce) 0 200 0 0 0 16 Total 100 200 0 0 24 24

*Open Elective subjects must be chosen from the list of open electives offered by various departments.

M. TECH. I YEAR I SEMESTER EMBEDDED SYSTEMS & VLSI DESIGN/VLSI AND EMBEDDED SYSTEMS/ ELECTRONICS DESIGN TECHNOLOGY.