JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

UNIT - I

Introduction: Schematic fundamentals, Layout design, Introduction to CMOS VLSI manufacturing processes, Layers and connectivity, Process design rules Significance of full custom IC design, layout design flows.

UNIT - II

Advanced techniques for specialized building blocks Standard cell libraries, Pad cells and Laser fuse cells, Advanced techniques for building blocks, Power grid Clock signals

UNIT - III

Interconnect routing. Interconnect layout design, Special electrical requirements, Layout design techniques to address electrical characteristics.

UNIT - IV

Layout considerations due to process constraints Large metal via implementations, Step coverage rules, Special design rules, Latch-up and Guard rings, Constructing the pad ring, Minimizing Stress effects.

UNIT - V

Proper layout CAD tools for layout, Planning tools, Layout generation tools, Support tools.

TEXT BOOKS:

• 1. Dan Clein, “CMOS IC Layout Concepts Methodologies and Tools”, Newnes, 2000.
• 2. Ray Alan Hastings, “The Art of Analog Layout”, 2nd Edition, Prentice Hall, 2006 M. TECH. – I YEAR – II SEMESTER VLSI/ VLSI DESIGN/VLSI SYSTEM DESIGN