JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

UNIT - I

Introduction to the System Approach: System Architecture, Components of the system, Hardware & Software, Processor Architectures, Memory and Addressing. System level interconnection, An approach for SOC Design, System Architecture and Complexity.

UNIT - II

Processors: Introduction , Processor Selection for SOC, Basic concepts in Processor Architecture, Basic concepts in Processor Micro Architecture, Basic elements in Instruction handling. Buffers: minimizing Pipeline Delays, Branches, More Robust Processors, Vector Processors and Vector Instructions extensions, VLIW Processors, Superscalar Processors.

UNIT - III

Memory Design for SOC: Overview of SOC external memory, Internal Memory, Size, Scratchpads and Cache memory, Cache Organization, Cache data, Write Policies, Strategies for line replacement at miss time, Types of Cache, Split – I, and D – Caches, Multilevel Caches, Virtual to real translation , SOC Memory System, Models of Simple Processor – memory interaction.

UNIT - IV

Interconnect Customization and Configuration: Inter Connect Architectures, Bus: Basic Architectures, SOC Standard Buses , Analytic Bus Models, Using the Bus model, Effects of Bus transactions and contention time. SOC Customization: An overview, Customizing Instruction Processor, Reconfiguration Technologies, Mapping design onto Reconfigurable devices, Instance- Specific design, Customizable Soft Processor, Reconfiguration - overhead analysis and trade-off analysis on reconfigurable Parallelism.

UNIT - V

Application Studies / Case Studies: SOC Design approach, AES algorithms, Design and evaluation, Image compression – JPEG compression.

TEXT BOOKS:

• 1. Michael J. Flynn and Wayne Luk, “Computer System Design System-on-Chip”, Wiley India Pvt. Ltd.
• 2. Steve Furber, “ARM System on Chip Architecture”, 2nd Edition, 2000, Addison Wesley Professional.

REFERENCE BOOKS:

st

• 1. Ricardo Reis, “Design of System on a Chip: Devices and Components”, 1 Edition, 2004, Springer
• 2. Jason Andrews, “Co-Verification of Hardware and Software for ARM System on Chip Design (Embedded Technology)”, Newnes, BK and CDROM.
• 3. Prakash Rashinkar, Peter Paterson and Leena Singh L, “System on Chip Verification – Methodologies and Techniques”, 2001, Kluwer Academic Publishers. M. TECH. – I YEAR – II SEMESTER SYSTEMS AND SIGNAL PROCESSING SIGNAL PROCESSING LAB – II

Note:

A. Minimum of 10 Experiments have to be conducted B. All Simulations are be carried out using MATLAB/DSP Processors/Labview Software & DSP Kits(or any other equivalent software)

• 1. Study of various addressing modes of DSP using simple programming examples
• 2. Generation of waveforms using recursive/filter methods
• 3. Sampling of input signal and display
• 4. Implementation of Linear and Circular Convolution for sinusoidal signals
• 5. Framing & windowing of speech signal.
• 6. Finding voiced & unvoiced detection for each frame of speech signal.
• 7. IIR Filter implementation using probe points
• 8. Implementation of FIR filters on DSP processor
• 9. Loop back using DSK kit
• 10. Real time signal enhancement using Adaptive Filter.
• 11. Representation of different Q-formats using GEL function
• 12. Verification of Finite word length effects (Overflow, Coefficient Quantization, Scaling and Saturation mode in DSP processors)
• 13. Image enhancement using spatial & frequency domain
• 14. Implementation of Image segmentation techniques
• 15. Extraction of frames from Video signal