JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

UNIT - I

Introduction to the System Approach: System Architecture, Components of the system, Hardware & Software, Processor Architectures, Memory and Addressing. System level interconnection, An approach for SOC Design, System Architecture and Complexity.

UNIT - II

Processors: Introduction , Processor Selection for SOC, Basic concepts in Processor Architecture, Basic concepts in Processor Micro Architecture, Basic elements in Instruction handling. Buffers: minimizing Pipeline Delays, Branches, More Robust Processors, Vector Processors and Vector Instructions extensions, VLIW Processors, Superscalar Processors.

UNIT - III

Memory Design for SOC: Overview of SOC external memory, Internal Memory, Size, Scratchpads and Cache memory, Cache Organization, Cache data, Write Policies, Strategies for line replacement at miss time, Types of Cache, Split – I, and D – Caches, Multilevel Caches, Virtual to real translation , SOC Memory System, Models of Simple Processor – memory interaction.

UNIT - IV

Interconnect Customization and Configuration: Inter Connect Architectures, Bus: Basic Architectures, SOC Standard Buses , Analytic Bus Models, Using the Bus model, Effects of Bus transactions and contention time. SOC Customization: An overview, Customizing Instruction Processor, Reconfiguration Technologies, Mapping design onto Reconfigurable devices, Instance- Specific design, Customizable Soft Processor, Reconfiguration - overhead analysis and trade-off analysis on reconfigurable Parallelism.

UNIT - V

Application Studies / Case Studies: SOC Design approach, AES algorithms, Design and evaluation, Image compression – JPEG compression.

TEXT BOOKS:

• 1. Michael J. Flynn and Wayne Luk, “Computer System Design System-on-Chip”, Wiley India Pvt. Ltd.
• 2. Steve Furber, “ARM System on Chip Architecture “, 2nd Edition, 2000, Addison Wesley Professional.

REFERENCE BOOKS:

st

• 1. Ricardo Reis, “”Design of System on a Chip: Devices and Components”, 1 Edition, 2004, Springer
• 2. Jason Andrews, “Co-Verification of Hardware and Software for ARM System on Chip Design (Embedded Technology)”, Newnes, BK and CDROM.
• 3. Prakash Rashinkar, Peter Paterson and Leena Singh L, “System on Chip Verification – Methodologies and Techniques”, 2001, Kluwer Academic Publishers. M. TECH. I YEAR II SEMESTER DIGITAL SYSTEMS & COMPUTER ELECTRONICS EMBEDDED SYSTEMS LAB Part - I a.
• i. Write a simple program to print “hello world”
• ii. Write a simple program to show a delay.
• iii. Write a program for counting the number of times that a switch is pressed & released.
• iv. Write a c program to test loop time outs.
• v. Write a c program to test hardware based timeout loops.
• vi. Illustrate the use of port header file (port M) using an interface consisting of a keypad and liquid crystal display.
• b. Write a program to create a portable hardware delay.
• c. Write a loop application to copy values from P1 to P2
• d. Develop a simple EOS showing traffic light sequencing.
• e. Write a program to drive SEOS using Timer 0. Part-II The following programs are to be implemented on ARM Processor
• 1. Simple assembly program for addition, Subtraction, Multiplication, Division, Operating Modes, System Calls and Interrupts, Loops, Branches.
• 2. Write an Assembly program to configure and control general purpose input/output (GPIO) port pins
• 3. To read digital values from external peripherals and execute them with the target board
• 4. Program for reading and writing of a file
• 5. To demonstrate time delay program using built in timer / counter feature on IDE environment
• 6. To demonstrate a simple interrupt handler and setting up a timer
• 7. Program to demonstrate a simple interrupt handler. Press button to generate an interrupt and trace the program flow with debug terminal
• 8. Program to interface 8 Bit LED and Switch Interface
• 9. Program to implement Buzzer Interface on IDE environment