JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

UNIT - I

Introduction to Verilog HDL: Verilog as HDL, Levels of Design Description, Concurrency, Simulation and Synthesis, Function Verification, Systems tasks, programming language interface, Module, Simulation and Synthesis tools. Language Constructs and Conventions: Introduction, Keywords, Identifiers, White Space Characters, Comments, Numbers, Strings, Logic values, Strengths, Data types, Scalars and Vectors, Parameters, Operators.

UNIT - II

Gate Level Modeling: Introduction, AND Gate Primitive, Module, Structure, Other Gate Primitives, Illustrative Examples, Tristate Gates, Array of Instances of Primitives, Design of Flip – Flops with Gate Primitives, Delays, Strengths and Construction Resolution, Net Types, Design of Basic Circuit. Modeling at Dataflow Level: Introduction, Continuous Assignment Structure, Delays and Continuous Assignments Assignment to Vectors, Operators.

UNIT - III

Behavioral Modeling: Introduction, Operations and Assignments, Functional Bifurcation, Initial Construct, Always Construct, Assignments with Delays, Wait Construct, Multiple Always Block, Designs at Behavioral Level, Blocking and Non-Blocking Assignments, The Case Statement, Simulation Flow if an if-Else Constructs, Assign- De-Assign Construct, Repeat Construct, for Loop, the Disable Construct, While Loop, For Ever Loop, Parallel Blocks, Force-Release, Construct, Event.

UNIT - IV

Switch Level Modeling: Basic Transistor Switches, CMOS Switches, Bi Directional Gates, Time Delays with Switch Primitives, Instantiation with Strengths and Delays, Strength Contention with Trireg Nets. System Tasks, Functions and Compiler Directives: Parameters, Path Delays, Module Parameters, System Tasks and Functions, File Based Tasks and Functions, Computer Directives, Hierarchical Access, User Defined Primitives.

UNIT - V

Sequential Circuit Description: Sequential Models – Feedback Model, Capacitive Model, Implicit Model, Basic Memory Components, Functional Register, Static Machine Coding, Sequential Synthesis. Component Test and Verification: Test Bench-Combinational Circuit Testing, Sequential Circuit Testing, Test Bench Techniques, Design Verification, Assertion Verification

TEXT BOOKS:

• 1. T R Padmanabhan, B.Bala Tripura Sundari, Design through Verilog HDL, 2009, Wiley. nd
• 2. Zainalabdien Navabi, Verilog Digital System Design, TMH,2 Edition,

REFERENCES:

nd

• 1. Stephen Brown, Zvonkoc Vranesic, “Fundamentals of Digital Logic with Verilog Design”, 2 Edition, 2010, TMH
• 2. Sunggu Lee, “ Digital Logic Design using Verilog, State Machine & Synthesis for FPGA,” Cengage Learning 2009
• 3. Samir Palnitkar, “Verilog HDL”, 2nd Edition, Pearson Education, 2009.
• 4. Michel D. Ciletti, “Advanced Digital Design with verilog HDL”, PHI, 2009. M. TECH. I YEAR II SEMESTER DIGITAL SYSTEMS & COMPUTER ELECTRONICS