JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

UNIT - I

Introduction to DSP: Typical DSP algorithms, DSP algorithms benefits, Representation of DSP algorithms. Pipelining and Parallel Processing: Introduction, Pipelining of FIR Digital filters, Parallel Processing, Pipelining and Parallel Processing for Low Power. Retiming: Introduction – Definitions and Properties – Solving System of Inequalities – Retiming Techniques.

UNIT - II

Folding and Unfolding: Folding: Introduction -Folding Transform - Register minimization Techniques – Register minimization in folded architectures – folding of multirate systems Unfolding: Introduction – An Algorithm for Unfolding – Properties of Unfolding – critical Path, Unfolding and Retiming – Applications of Unfolding

UNIT - III

Systolic Architecture Design: Introduction – Systolic Array Design Methodology – FIR Systolic Arrays – Selection of Scheduling Vector – Matrix Multiplication and 2D Systolic Array Design – Systolic Design for Space Representations contain Delays

UNIT - IV

Fast Convolution: Introduction – Cook-Toom Algorithm – Winogard algorithm – Iterated Convolution – Cyclic Convolution – Design of Fast Convolution algorithm by Inspection

UNIT - V

Low Power Design: Scaling Vs Power Consumption –Power Analysis, Power Reduction techniques – Power Estimation Approaches. Programmable DSP: Evaluation of Programmable Digital Signal Processors, DSP Processors for Mobile and Wireless Communications, Processors for Multimedia Signal Processing

TEXT BOOKS:

• 1. Keshab K. Parthi, “VLSI Digital Signal Processing- System Design and Implementation”, 1998, Wiley Inter Science.
• 2. Kung S. Y, H. J. While House, T. Kailath, “VLSI and Modern Signal processing”, 1985, Prentice Hall.

REFERENCE BOOKS:

• 1. Jose E. France, Yannis Tsividis, “Design of Analog – Digital VLSI Circuits for Telecommunications and Signal Processing”, 1994, Prentice Hall.
• 2. Medisetti V. K, “VLSI Digital Signal Processing”, 1995, IEEE Press (NY), USA.