JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

Course Outcomes

At the end of this course, students will be able to

• 1. Fundamentals of CAD tools for modelling, design, test and verification of VLSI systems.
• 2. Study of various phases of CAD, including simulation, physical design, test and verification.
• 3. Demonstrate knowledge of computational algorithms and tools for CAD.

UNIT - I

Introduction to VLSI Methodologies –Design and Fabrication of VLSI Devices, Fabrication Process and its impact on Design.

UNIT - II

VLSI design automation tools – Data structures and basic algorithms, graph theory and computational complexity, tractable and intractable problems.

UNIT - III

General purpose methods for combinational optimization – partitioning, floor planning and pin assignment, placement, routing.

UNIT - IV

Simulation – logic synthesis, verification, high level Synthesis.

UNIT - V

MCMS-VHDL-Verilog-implementation of simple circuits using VHDL

REFERENCES:

• 1. N.A. Sherwani, “Algorithms for VLSI Physical Design Automation”.
• 2. S.H. Gerez, “Algorithms for VLSI Design Automation”. R19 M. TECH. ES & VLSI DESIGN/VLSI & ES M.TECH.- I YEAR- I SEMESTER EMBEDDED SYSTEMS & VLSI DESIGN/VLSI & EMBEDDED SYSTEMS