JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

Course Outcomes

At the end of this course, students will be able to

• 1. Familiarity of Front end design and verification techniques and create reusable test environments.
• 2. Verify increasingly complex designs more efficiently and effectively.
• 3. Use EDA tools like Cadence, Mentor Graphics.

UNIT - I

Revision of basic Digital systems: Combinational Circuits, Sequential Circuits, Logic families Synchronous FSM and asynchronous design, Metastability, Clock distribution and issues, basic building blocks like PWM module, pre-fetch unit, programmable counter, FIFO, Booth's multiplier, ALU, Barrel shifter etc.

UNIT - II

Verilog/VHDL Comparisons and Guidelines, Verilog: HDL fundamentals, simulation, and test- bench design, Examples of Verilog codes for combinational and sequential logic, Verilog AMS

UNIT - III

System Verilog and Verification: Verification guidelines, Data types, procedural statements and routines, connecting the test bench and design, Assertions, Basic OOP concepts, Randomization, Introduction to basic scripting language: Perl, Tcl/Tk

UNIT - IV

Current challenges in physical design: Roots of challenges, Delays: Wire load models Generic PD flow, Challenges in PD flow at different steps, SI Challenge - Noise & Crosstalk, IR Drop, Process effects: Process Antenna Effect & Electromigration

UNIT - V

Programmable Logic Devices: Introduction, Evolution: PROM, PLA, PAL, Architecture of PAL's, Applications, Programming PLD's, FPGA with technology: Antifuse, SRAM, EPROM, MUX, FPGA structures, and ASIC Design Flows, Programmable Interconnections, Coarse grained reconfigurable devices

TEXTBOOKS:

• 1. Douglas Smith, “HDL Chip Design: A Practical Guide for Designing, Synthesizing & Simulating ASICs & FPGAs Using VHDL or Verilog”, Doone publications, 1998.
• 2. Samir Palnitkar, “Verilog HDL: A guide to Digital Design and Synthesis”, Prentice Hall, 2nd Edition, 2003.

REFERENCES:

• 1. Doug Amos, Austin Lesea, Rene Richter, “FPGA based Prototyping Methodology Manual”, Synopsys Press, 2011.
• 2. Christophe Bobda, “Introduction to Reconfigurable Computing, Architectures, Algorithms and Applications”, Springer, 2007.
• 3. Janick Bergeron, “Writing Testbenches: Functional Verification of HDL Models”, Second Edition, Springer, 2003. R19 M.Tech. VLSI/VLSI Design/VLSI System Design M.TECH.- I YEAR- I SEMESTER VLSI /VLSI DESIGN/VLSI SYSTEM DESIGN