JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

Course Objectives:

• To provide familiarity with hardware description language Verilog HDL for modelling of combinational and sequential circuits.
• To understand the role of functional simulator in the validating the functionality of designed circuits.
• To understand the Synthesis of a designed digital circuits.
• To introduce the process of implementation of digital circuits on FPGA kits.

Course Outcomes

After completing this course the student will be able to

• Apply CAD tools for the design of digital circuits.
• Appreciate the process of synthesizing a given digital circuits.
• Implement the specified digital circuits using FPGA. Implementation of the following designs on FPGA using Verilog HDL:
• 1. 8:1 Mux/Demux, Full Adder, 8-bit Magnitude comparator, Encoder/decoder, Priority encoder, Parity generator
• 2. Code converters
• 3. D-FF, 4-bit Shift registers (SISO, SIPO, PISO, bidirectional), 3-bit Synchronous Counters.
• 4. Sequence generator/detectors, Synchronous FSM – Mealy and Moore machines.
• 5. Vending machines - Traffic Light controller, ATM, elevator control.
• 6. PCI Bus &Arbiter.
• 7. Single and Dual port SRAM
• 8. Arithmetic circuits like serial adder/ subtractor, parallel adder/subtractor, serial/parallel multiplier. R19 M.Tech. VLSI/VLSI Design/VLSI System Design M.TECH.- I YEAR- I SEMESTER VLSI/VLSI DESIGN/VLSI SYSTEM DESIGN