JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

Pre-Requisite

Switching Theory and Logic Design

Course Objectives:

• 1. To provide extended knowledge of digital logic circuits in the form of state model approach.
• 2. To provide an overview of system design approach using programmable logic devices.
• 3. To provide and understand of fault models and test methods.
• 4. To get exposed to the various architectural features of CPLDS and FPGAS.
• 5. To learn the methods and techniques of CPLD & FPGA design with EDA tools.
• 6. To expose software tools used for design process with the help of case studies.

Course Outcomes:

• 1. To understands the minimization of Finite state machine.
• 2. To exposes the design approaches using ROM’s, PAL’s and PLA’s.
• 3. To provide in depth understanding of Fault models.
• 4. To understands test pattern generation techniques for fault detection.
• 5. To design fault diagnosis in sequential circuits.
• 6. To provide exposure to various CPLDS and FPGAS available in market.
• 7. To acquire knowledge in one hot state machine design applicable to FPGA.
• 8. To get exposure to EDA tools.
• 9. To provide understanding in the design of flow using case studies.

UNIT - I

Programmable Logic Devices: The concept of programmable Logic Devices, SPLDs, PAL devices, PLA devices, GAL devices, CPLD-Architecture, Xilinx CPLDs- Altera CPLDs, FPGAs-FPGA technology, architecture, virtex CLB and slice- Stratix LAB and ALM-RAM Blocks, DSP Blocks, Clock Management, I/O standards, Additional features. [TEXTBOOK-1]

UNIT - II

Analysis and derivation of clocked sequential circuits with state graphs and tables: A sequential parity checker, Analysis by signal tracing and timing charts-state tables and graphs- general models for sequential circuits, Design of a sequence detector, More Complex design problems, Guidelines for construction of state graphs, serial data conversion, Alphanumeric state graph notation. [TEXTBOOK-2]

UNIT - III

Sequential circuit Design: Design procedure for sequential circuits-design example, Code converter, Design of Iterative circuits, Design of a comparator, Design of sequential circuits using ROMs and PLAs, Sequential circuit design using CPLDs, Sequential circuit design using FPGAs, Simulation and testing of Sequential circuits, Overview of computer Aided Design. [TEXTBOOK-2]

UNIT - IV

Fault Modeling and Test Pattern Generation: Logic Fault Model, Fault detection & redundancy, Fault equivalence and fault location, Fault dominance, Single stuck at fault model, multiple Stuck at Fault models, Bridging Fault model.

R19 M.TECH. DIGITAL SYSTEMS AND COMPUTER ELECTRONICS

Fault diagnosis of combinational circuits by conventional methods, path sensitization techniques, Boolean difference method, KOHAVI algorithm, Test algorithms-D algorithm, Random testing, transition count testing, signature analysis and test bridging faults. [TEXTBOOK-3 & Ref.1]

UNIT - V

Fault Diagnosis in sequential circuits: Circuit Test Approach, Transition check Approach, State identification and fault detection experiment, Machine identification, Design of fault detection experiment. [Ref.1]

TEXTBOOKS

• 1. Digital Electronics and design with VHDL- Volnei A. Pedroni, Elsevier publications.
• 2. Fundamentals of Logic Design-Charles H.Roth,Jr. -5th Ed.,Cengage Learning.
• 3. Logic Design Theory-N.N.Biswas,PHI.

REFERENCES

• 1. Digital Circuits and Logic Design-Samuel C.LEE,PHI, 2008.
• 2. Digital System Design using programmable logic devices- Parag K.Lala, BS publications. R19 M.TECH. DIGITAL SYSTEMS AND COMPUTER ELECTRONICS M.TECH.- I YEAR- I SEMESTER DIGITAL SYSTEMS & COMPUTER ELECTRONICS