JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

Course Outcomes:

• 1. At the end of this course, students will be able to Identify and formalize architectural level characterization of P-DSP hardware
• 2. Ability to design, programming (assembly and C), and testing code using Code Composer Studio environment
• 3. Deployment of DSP hardware for Control, Audio and Video Signal processing applications Understanding of major areas and challenges in DSP based embedded systems

UNIT - I

Programmable DSP Hardware: Processing Architectures (von Neumann, Harvard), DSP core algorithms (FIR, IIR, Convolution, Correlation, FFT), IEEE standard for Fixed and Floating Point Computations, Special Architectures Modules used in Digital Signal Processors (like MAC unit, Barrel shifters), On-Chip peripherals, DSP benchmarking.

UNIT - II

Structural and Architectural Considerations: Parallelism in DSP processing, Texas Instruments TMS320 Digital Signal Processor Families, Fixed Point TI DSP Processors: TMS320C1X and TMS320C2X Family,TMS320C25 –Internal Architecture, Arithmetic and Logic Unit, Auxiliary Registers, Addressing Modes (Immediate, Direct and Indirect, Bit-reverse Addressing), Basics of TMS320C54x and C55x Families in respect of Architecture improvements and new applications fields, TMS320C5416 DSP Architecture, Memory Map, Interrupt System, Peripheral Devices, Illustrative Examples for assembly coding.

UNIT - III

VLIW Architecture: Current DSP Architectures, GPUs as an alternative to DSP Processors, TMS320C6X Family, Addressing Modes, Replacement of MAC unit by ILP, Detailed study of ISA, Assembly Language Programming, Code Composer Studio, Mixed Cand Assembly Language programming, On-chip peripherals, Simple applications developments as an embedded environment.

UNIT - IV

Multi-core DSPs: Introduction to Multi-core computing and applicability for DSP hardware, Concept of threads, introduction to P-thread, mutex and similar concepts, heterogeneous and homogenous multi- core systems.

UNIT - V

Shared Memory parallel programming –OpenMP approach of parallel programming, PRAGMA directives, OpenMP Constructs for work sharing like for loop, sections, TI TMS320C6678 (Eight Core subsystem).

REFERENCES:

• 1. M. Sasikumar, D. Shikhare, Ravi Prakash, “Introduction to Parallel Processing”, 1st Edition, PHI, 2006.
• 2. Fayez Gebali, “Algorithms and Parallel Computing”,1st Edition, John Wiley & Sons, 2011
• 3. Rohit Chandra, Ramesh Menon, Leo Dagum, David Kohr, Dror Maydan, Jeff McDonald, “Parallel Programming in OpenMP”, 1st Edition, Morgan Kaufman,2000. R19 M.Tech. VLSI/VLSI Design/VLSI System Design
• 4. Ann Melnichuk, Long Talk, “Multicore Embedded systems”, 1st Edition, CRC Press,2010.
• 5. Wayne Wolf, “High Performance Embedded Computing: Architectures, Applications and Methodologies”, 1st Edition, Morgan Kaufman, 2006.
• 6. E.S. Gopi, “Algorithmic Collections for Digital Signal Processing Applications Using MATLAB”, 1st Edition, Springer Netherlands,2007. R19 M.Tech. VLSI/VLSI Design/VLSI System Design M.TECH.- I YEAR- I SEMESTER VLSI/VLSI DESIGN/VLSI SYSTEM DESIGN