JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

Overview

• 4. Understand the significance of Switching circuits and characteristics of Wired LANs

UNIT - I

Data Communications, Networks and Network Types, Internet History, Standards and Administration, Protocol Layering, TCP/IP protocol suite, OSI Model. Digital Data Transmission, DTE-DCE interface. Data Link Layer: Introduction, Data Link Layer, Nodes and Links, Services, Categories of Links, sub layers, Link Layer Addressing, Address Resolution Protocol.

UNIT - II

Error Detection and Correction:Types of Errors, Redundancy, detection versus correction, Coding Block Coding: Error Detection, Vertical redundancy cheeks, longitudinal redundancy cheeks, Error Correction, Error correction single bit, Hamming code. Cyclic Codes Cyclic Redundancy Check, Polynomials, Cyclic Code Encoder Using Polynomials, Cyclic Code Analysis, Advantage of Cyclic Codes, Checksum Data Link Control: DLC Services, Data Link Layer Protocols, HDLC, Point to Point Protocol

UNIT - III

Media Access Control (MAC) Sub Layer: Random Access, ALOHA, Carrier Sense Multiple Access (CSMA), Carrier Sense Multiple Access with Collision Detection (CSMA/CD), Carrier Sense Multiple Access with Collision Avoidance (CSMA/CA),Controlled Access- Reservation, Polling- Token Passing, Channelization - Frequency Division Multiple Access (FDMA), Time - Division Multiple Access (TDMA), Code - Division Multiple Access (CDMA). Wired LANS: Ethernet Protocol, Standard Ethernet, Fast Ethernet, Gigabit Ethernet, 10 Giga bit Ethernet

UNIT - IV

Switching: Introduction to Switching, Circuit Switched Networks, Packet Switching, Structure of switch Multiplexing: Multiplexing, Frequency Division Multiplexing, Time Division Multiplexing.

R19 M.TECH. DIGITAL SYSTEMS AND COMPUTER ELECTRONICS

Spectrum Spreading: Spread Spectrum-Frequency Hopping Spread Spectrum and Direct Sequence Spread Spectrum Connecting devices: Passive Hubs, Repeaters, Active Hubs, Bridges, Two Layer Switches, Routers, Three Layer Switches, Gateway, Backbone Networks.

UNIT - V

Networks Layer: Packetizing, Routing and Forwarding, Packet Switching, Network Layer Performance, IPv4 Address, Address Space, Classful Addressing, Classless Addressing, Dynamic Host Configuration Protocol (DHCP), Network Address Resolution(NATF), Forwarding of IP Packets, Forwarding based on Destination Address, Forwarding based on Label, Routing as Packet Switches. Unicast Routing: Introduction, Routing Algorithms-Distance Vector Routing, Link State Routing, Path Vector Routing, Unicast Routing Protocols- Routing Information Protocol(RIP), Open Short Path First .

TEXT BOOKS

• 1. Data Communications and Networking - B. A. Forouzan, 5th Ed., TMH, 2013.
• 2. Data and Computer Communications - William Stallings, 8th Ed., PHI, 2007.

REFERENCES

• 1. Data Communications and Computer Networks - Prakash C. Gupta, PHI, 2006.
• 2. Data Communications and Networking - B. A. Forouzan, 2nd Ed., TMH, 2013.
• 3. Data Communications and Computer Networks- Brijendra Singh, 2nd Ed., 2008. R19 M.TECH. DIGITAL SYSTEMS AND COMPUTER ELECTRONICS M.TECH.- I YEAR- I SEMESTER DIGITAL SYSTEMS & COMPUTER ELECTRONICS DIGITAL SYSTEM DESIGN LAB (Lab – I) Part –I: Programming can be done using any complier. Down load the programs on FPGA/CPLD boards and performance testing may be done using pattern generator (32 channels) and logic analyzer apart from verification by simulation with any of the front end tools.
• 1. HDL code to realize all the logic gates
• 2. Design and Simulation of adder, Serial Binary Adder, Multi Precession Adder, Carry
• 3. Look Ahead Adder.
• 4. Design of 2-to-4 decoder
• 5. Design of 8-to-3 encoder (without and with parity)
• 6. Design of 8-to-1 multiplexer
• 7. Design of 4 bit binary to gray converter
• 8. Design of Multiplexer/ Demultiplexer, comparator
• 9. Design of Full adder using 3 modeling styles
• 10. Design of flip flops: SR, D, JK, T
• 11. Design of 4-bit binary, BCD counters (synchronous/ asynchronous reset) or any sequence counter
• 12. Design of a N- bit Register of Serial- in Serial –out, Serial in parallel out, Parallel in
• 13. Serial out and Parallel in Parallel Out.
• 14. Design of Sequence Detector (Finite State Machine- Mealy and Moore Machines).
• 15. Design of 4- Bit Multiplier, Divider.
• 16. Design of ALU to Perform – ADD, SUB, AND-OR, 1’s and 2’s Compliment,
• 17. Multiplication, and Division.
• 18. Design of Finite State Machine.
• 19. Implementing the above designs on Xilinx/Altera/Cypress/equivalent based FPGA/CPLD kits . Part –II:
• 1. Static and Dynamic Characteristics of CMOS Inverter
• 2. Implementation of EX-OR gate using complementary CMOS, Psedo-NMOS, Dynamic and domino logic style
• 3. Implementation of Full Adder using Transmission Gates R19 M.TECH. DIGITAL SYSTEMS AND COMPUTER ELECTRONICS M.TECH.- I YEAR- I SEMESTER DIGITAL SYSTEMS & COMPUTER ELECTRONICS