M.Tech I Year II Semester (R19)
At the end of the course, students will be able to:
Introduction to VLSI Physical Design Automation: Design Representation, VLSI Design Styles, and VLSI Physical Design automation.
Partitioning, Floor planning, Pin Assignment, Standard cell, Performance issues in circuit layout, delay models, Layout styles.
Placement: Problem formulation, classification, Simulation based placement algorithms, Partitioning based placement algorithms, Time driven and performance driven placement.
Global routing: Problem formulation, classification of global routing, Maze routing algorithms, Line- Probe algorithms, and shortest path based algorithms, Steiner Tree based algorithms, Integer programming based approach, Performance driven routing. Detailed Routing: Problem formulation, classification, Single layer, two layer, three layer and Multi- Layer channel routing, Algorithms, Switch box routing.
Over the Cell Routing - Single layer and two-layer routing: Over the cell routing, Two Layer, Three Layer and Multi-Layer OTC Routing. Via Minimization: Constraint and Unconstrained via minimization. Clock and Power Routing: Clocking schemes, design considerations for the clock, Problem formulation, Clock routing algorithms, Skew and Delay reduction by Pin Assignment, Multiple clock routing, Power and Ground Routing
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