JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

Course Outcomes

At the end of the course, students will demonstrate the ability to:

• 1. Familiarity of Finite State Machines, RTL design using reconfigurable logic.
• 2. Design and develop IP cores and Prototypes with performance guarantees
• 3. Use EDA tools like Cadence, Mentor Graphics and Xilinx

UNIT - I

Top down approach to design, Design of FSMs (Synchronous and asynchronous), Static timing analysis, Meta-stability, Clock issues, Need and design strategies for multi-clock domain designs.

UNIT - II

Design entry by Verilog/VHDL/FSM, Verilog AMS.

UNIT - III

Programmable Logic Devices, Introduction to ASIC Design Flow, FPGA, SoC, Floor planning, Placement, Clock tree synthesis, Routing, Physical verification, Power analysis, ESD protection.

UNIT - IV

Design for performance, Low power VLSI design techniques. Design for testability.

UNIT - V

IP and Prototyping: IP in various forms: RTL Source, Encrypted Source, Soft IP, Netlist, Physical IP, Use of external hard IP during prototyping

TEXTBOOKS:

• 1. Richard S. Sandige, “Modern Digital Design”, MGH, International Editions.
• 2. Donald D Givone, “Digital principles and Design”, TMH

REFERENCES:

• 1. Charles Roth, Jr. and Lizy K John, “Digital System Design using VHDL”, Cengage Learning.
• 2. Samir Palnitkar, “Verilog HDL, a guide to digital design and synthesis”, Prentice Hall.
• 3. Doug Amos, Austin Lesea, Rene Richter, “FPGA based prototyping methodology manual”, Xilinx.
• 4. Bob Zeidman, “Designing with FPGAs & CPLDs”, CMP Books. R19 M. TECH. ES & VLSI DESIGN/VLSI & ES M.TECH. I YEAR - I SEMESTER EMBEDDED SYSTEMS & VLSI DESIGN/VLSI & EMBEDDED SYSTEMS