JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

Course Outcomes

At the end of the laboratory work, students will be able to:

• 1. Identify, formulate, solve and implement problems in signal processing, communication systems etc using RTL design tools.
• 2. Use EDA tools like Cadence, Mentor Graphics and Xilinx or equivalent tools

List of Experiments:

• 1. Verilog implementation of 8:1 Mux/Demux, Full Adder, 8-bit Magnitude comparator, Enr/der, Priority enr, D-FF, 4-bit Shift registers (SISO, SIPO, PISO, bidirectional), 3-bit Synchronous Counters, Binary to Gray converter, Parity generator.
• 2. Sequence generator/detectors, Synchronous FSM – Mealy and Moore machines.
• 3. Vending machines - Traffic Light controller, ATM, elevator control.
• 4. PCI Bus & arbiter and downloading on FPGA.
• 5. UART/ USART implementation in Verilog.
• 6. Realization of single port SRAM in Verilog.
• 7. Verilog implementation of Arithmetic circuits like serial adder/ subtractor, parallel adder/subtractor, serial/parallel multiplier.
• 8. Discrete Fourier transform/Fast Fourier Transform algorithm in Verilog. R19 M. TECH. ES & VLSI DESIGN/VLSI & ES M.TECH.- I YEAR- I SEMESTER EMBEDDED SYSTEMS & VLSI DESIGN/VLSI & EMBEDDED SYSTEMS