JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

UNIT - I

Fading Channels and Diversity Techniques: Wireless channels – Error/Outage probability over fading channels – Diversity techniques – Channel coding as a means of time diversity – Multiple antennas in wireless communications.

UNIT - II

Capacity and Information Rates of MIMO Channels: Capacity and Information rates of noisy, AWGN and fading channels – Capacity of MIMO channels – Capacity of non-coherent MIMO channels – Constrained signaling for MIMO communications.

UNIT - III

Space-Time Block and Trellis Codes: Transmit diversity with two antennas: The Alamouti scheme – Orthogonal. and Quasi-orthogonal space-time block codes – Linear dispersion codes – Generic space-time trellis codes – Basic space-time code design principles – Representation of space-time trellis codes for PSK constellation – Performance analysis for space-time trellis codes – Comparison of space-time block and trellis codes.

UNIT - IV

Concatenated Codes and Iterative Decoding: Development of concatenated codes – Concatenated codes for AWGN and MIMO channels – Turbo coded modulation for MIMO channels – Concatenated space-time block coding.

UNIT - V

Space-Time Coding for Frequency Selective Fading Channels: MIMO frequency-selective channels – Capacity and Information rates of MIMO FS fading channels – Space-time coding and Channel detection for MIMO FS channels – MIMO OFDM systems.

TEXT BOOKS:

• 1. Tolga M. Duman and Ali Ghrayeb, “Coding for MIMO Communication systems”, John Wiley & Sons, West Sussex, England, 2007.
• 2. A. B. Gershman and N.D. Sidiropoulus, “Space-time processing for MIMO Communications”, Wiley, Hoboken, NJ, USA, 2005.

REFERENCES:

• 1. E.G. Larsson and P. Stoica, “Space-time block coding for Wireless communications”, Cambridge University Press, 2003.
• 2. M. Janakiraman, “Space-time codes and MIMO systems”, Artech House, 2004.
• 3. H. Jafarkhani, “Space-time coding: Theory & Practice”, Cambridge University Press, 2005. R19 M.Tech. DECE/DECS M.TECH.- I YEAR- I SEMESTER DECE/DECS DIGITAL SYSTEM DESIGN LAB (Lab – I) Part –I Programming can be done using any complier. Down load the programs on FPGA/CPLD boards and performance testing may be done using pattern generator (32 channels) and logic analyzer apart from verification by simulation with any of the front-end tools.
• 1. HDL code to realize all the logic gates
• 2. Design and Simulation of adder, Serial Binary Adder, Multi Precession Adder, Carry
• 3. Look Ahead Adder.
• 4. Design of 2-to-4 decoder
• 5. Design of 8-to-3 encoder (without and with parity)
• 6. Design of 8-to-1 multiplexer
• 7. Design of 4 bit binary to gray converter
• 8. Design of Multiplexer/ Demultiplexer, comparator
• 9. Design of Full adder using 3 modeling styles
• 10. Design of flip flops: SR, D, JK, T
• 11. Design of 4-bit binary, BCD counters (synchronous/ asynchronous reset) or any sequence counter
• 12. Design of a N- bit Register of Serial- in Serial –out, Serial in parallel out, Parallel in
• 13. Serial out and Parallel in Parallel Out.
• 14. Design of Sequence Detector (Finite State Machine- Mealy and Moore Machines).
• 15. Design of 4- Bit Multiplier, Divider.
• 16. Design of ALU to Perform – ADD, SUB, AND-OR, 1’s and 2’s Compliment,
• 17. Multiplication, and Division.
• 18. Design of Finite State Machine.
• 19. Implementing the above designs on Xilinx/Altera/Cypress/equivalent based FPGA/CPLD kits. Part –II
• 1. Static and Dynamic Characteristics of CMOS Inverter
• 2. Implementation of EX-OR gate using complementary CMOS, Psedo-NMOS, Dynamic and domino logic style
• 3. Implementation of Full Adder using Transmission Gates R19 M.Tech. DECE/DECS M.TECH.- I YEAR- I SEMESTER DECE/DECS