JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

Course Outcomes

At the end of the laboratory work, students will be able to:

• 1. Design analog Circuit using CMOS.
• 2. Use EDA tools like Cadence, Mentor Graphics and other opensource software tools like Ngspice

List of Experiments:

• 1) Use VDD = 1.8V for 0.18 um CMOS process, VDD = 1.3V for 0.13 um CMOS Process and VDD = 1V for 0.09 um CMOS Process.
• a) Plot ID vs. VGS at different drain voltages for NMOS, PMOS.
• b) Plot ID vs. VGS at particular drain voltage (low) for NMOS, PMOS and determine Vt.
• c) Plot log ID vs. VGS at particular gate voltage (high) for NMOS, PMOS and determine IOFF and sub-threshold slope.
• d) Plot ID vs. VDS at different gate voltages for NMOS, PMOS and determine Channel length modulation factor.
• e) Extract Vth of NMOS/PMOS transistors (short channel and long channel). Use VDS = 30 mV To extract Vth use the following procedure.
• i. Plot gm vs VGS using NGSPICE and obtain peak gm point.
• ii. Plot y= ID/(gm)1/2 as a function of VGS using Ngspice.
• iii. Use Ngspice to plot tangent line passing through peak gm point in y (VGS) plane and determine Vth.
• f) Plot ID vs. VDS at different drain voltages for NMOS, PMOS, plot DC load line and calculate gm, gds, gm/gds, and unity gain frequency. Tabulate your result according to technologies and comment on it.
• 2) Use VDD = 1.8V for 0.18 um CMOS process, VDD =1.2V for 0.13 um CMOS Process and VDD = 1V for 0.09 um CMOS Process.
• a) Perform the following
• i. Plot VTC curve for CMOS inverter and thereon plot dVout vs. dVin and determine transition voltage and gain g. Calculate VIL, VIH, NMH, NML for the inverter.
• ii. Plot VTC for CMOS inverter with varying VDD.
• iii. Plot VTC for CMOS inverter with varying device ratio.
• b) Perform transient analysis of CMOS inverter with no load and with load and determine tpHL, tpLH, 20%-to-80% tr and 80%-to-20% tf. (use VPULSE = 2V, Cload =50 fF)
• c) Perform AC analysis of CMOS inverter with fanout 0 and fanout 1. (Use Cin= 0.012 pF, Cload = 4pF, Rload = k)
• 3) Use Ngspice to build a three stage and five stage ring oscillator circuit in 0.18 um and 0.13 um technology and compare its frequencies and time period.
• 4) Perform the following
• a) Draw small signal voltage gain of the minimum-size inverter in 0.18 um and 0.13 um technology as a function of input DC voltage. Determine the small signal voltage gain at the switching point using Ngspice and compare the values for 0.18 um and 0.13 um process.
• b) Consider a simple CS amplifier with active load, as explained in the lecture, with NMOS transistor MN as driver and PMOS transistor MP as load, in 0.18 um technology. (W/L) MN=5, (W/L) MP=10 and L= 0.5 um for both transistors.
• i. Establish a test bench, as explained in the lecture, to achieve VDSQ = VDD/2.
• ii. Calculate input bias voltage if bias current = 50 uA.
• iii. Use Ngspice and obtain the bias current. Compare its value with 50 uA.
• iv. Determine small signal voltage gain, - 3 dB BW and GBW of the amplifier using small signal analysis in Ngspice (consider 30fF load capacitance).
• v. Plot step response of the amplifier for input pulse amplitude of 0.1V. Derive time constant of the output and compare it with the time constant resulted from -3dB BW
• vi. Use Ngspice to determine input voltage range of the amplifier
• 5) Three OP-AMP INA. Vdd = 1.8V Vss = 0V, CAD tool: Mentor Graphics DA.

Note

Adjust accuracy options of the simulator (setup->options in GUI). Use proper values of

resistors to get a three OP-AMP INA with differential-mode voltage gain=10. Consider voltage gain=2 for the first stage and voltage gain=5 for the second stage.

• i. Draw the schematic of op-amp macro model.
• ii. Draw the schematic of INA.
• iii. Obtain parameters of the op-amp macro model such that a. low-frequency voltage gain =5 x 104, b. unity gain BW (fu) =500 KHz, c. input capacitance = 0.2 pF, d. output resistance =, e. CMRR=120 dB
• iv. Draw schematic diagram of CMRR simulation setup.
• v. Simulate CMRR of INA using AC analysis (it's expected to be around 6 dB below CMRR of OP-AMP).
• vi. Plot CMRR of the INA versus resistor mismatches (for resistors of second stage only) changing from -5% to +5% (use AC analysis). Generate a separate plot for mismatch in each resistor pair. Explain how CMRR of OPAMP changes with resistor mismatches.
• vii. Repeat (iii) to (vi) by considering CMRR of all OP-AMPs to be 90 dB.
• 6) Technology: UMC 0.18 um, VDD=1.8V. Use MAGIC or Microwind.
• a) Draw layout of a minimum size inverter in UMC 0.18um technology using MAGIC Station layout editor. Use that inverter as a cell and lay out three cascaded minimum-sized inverters. Use M1 as interconnect line between inverters.
• b) Run DRC, LVS and RC extraction. Make sure there is no DRC error. Extract the netlist.
• c) Use extracted netlist and obtain tPHL, tPLH for the middle inverter using Eldo.
• d) Use interconnect length obtained and connect the second and third inverter. Extract the new netlist and obtain tPHL and tPLH of the middle inverter. Compare new values of delay times with corresponding values obtained in part ‘c’ M.TECH.- I YEAR- II SEMESTER EMBEDDED SYSTEMS & VLSI DESIGN/VLSI & EMBEDDED SYSTEMS