JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

Course Objectives:

• 1. To known how to select the suitable Buses for different applications
• 2. To known the architecture of CAN and applications
• 3. To understand the use of PCIe, USB etc.,
• 4. To known the serial communication protocol

Course Outcomes

At the end of the course, students will be able to:

• 1. Select a particular serial bus suitable for a particularapplication.
• 2. Develop APIs for configuration, reading and writing data onto serialbus.
• 3. Design and develop peripherals that can be interfaced to desired serialbus.

UNIT - I

Serial Busses- Physical interface, Data and Control signals, features, limitations and applications of RS232, RS485, I2C, SPI

UNIT - II

CAN - Architecture, Data transmission, Layers, Frame formats, applications

UNIT - III

PCIe - Revisions, Configuration space, Hardware protocols, applications

UNIT - IV

USB - Transfer types, enumeration, Descriptor types and contents, Device driver

UNIT - V

Data Streaming Serial Communication Protocol - Serial Front Panel Data Port (SFPDP) using fiber optic and copper cable

TEXT BOOKS:

• 1. Jan Axelson, “Serial Port Complete - COM Ports, USB Virtual Com Ports, and Ports for Embedded Systems”, Lakeview Research, 2ndEdition
• 2. Jan Axelson, “USB Complete”, PenramPublications
• 3. Mike Jackson, Ravi Budruk, “PCI Express Technology”, MindsharePress

REFERENCE BOOKS:

• 1. Wilfried Voss, “A Comprehensible Guide to Controller Area Network”, Copperhill Media Corporation, 2nd Edition,2005.
• 2. Serial Front Panel Draft Standard VITA 17.1 –200x
• 3. Technical references on www.can-cia.org, http://www.pcisig.com/ www.pcisig.com, http://www.usb.org/ www.usb.org M.TECH.- I YEAR- I SEMESTER DIGITAL SYSTEMS & COMPUTER ELECTRONICS DIGITAL SYSTEM DESIGN WITH FPGAs LAB (Lab – I) Part -I: Programming can be done using any complier. Down load the programs on FPGA/CPLD boards and performance testing may be done using pattern generator (32 channels) and logic analyzer apart from verification by simulation with any of the front end tools. List of Assignments:
• 1. HDL code to realize all the logic gates
• 2. Design and Simulation of Full Adder, Serial Binary Adder, Multi Precession Adder, Carry Look Ahead Adder.
• 3. Design of Combinational circuit using Decoders.
• 4. Design of Combinational circuit using encoder (without and with parity).
• 5. Design of Combinational circuit using multiplexer.
• 6. Design of 4 bit binary to gray converter using MUX or Decoders.
• 7. Design of Multiplexer/ Demultiplexer, comparator in all 3 styles.
• 8. Modelling of an Edge triggered and Level triggered FFs : D, SR, JK
• 9. Design of 4-bit binary, BCD counters (synchronous/ asynchronous reset) or any sequence counter
• 10. Design of a N- bit Register of Serial- in Serial –out, Serial in parallel out, Parallel in Serial out and Parallel in Parallel Out using different FFs.
• 11. Design of Sequence Detector (Finite State Machine- Mealy and Moore Machines).
• 12. Design of 4- Bit Multiplier, Divider.
• 13. Design of ALU to Perform – ADD, SUB, AND-OR, 1’s and 2’s Compliment,
• 14. Implementing the above designs on FPGA kits. M.TECH.- I YEAR- I SEMESTER DIGITAL SYSTEMS & COMPUTER ELECTRONICS