JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

Pre-Requisite

Switching Theory and Logic Design

Course Objectives:

• 1. To provide extended knowledge of digital logic circuits in the form of state model approach.
• 2. To provide an overview of system design approach using programmable logic devices.
• 3. To provide and understand of fault models and test methods.
• 4. To get exposed to the various architectural features of CPLDS and FPGAS.
• 5. To learn the methods and techniques of CPLD & FPGA design with EDA tools.
• 6. To expose software tools used for design process with the help of case studies.

Course Outcomes:

• 1. To exposes the design approaches using FPGAs.
• 2. To provide in depth understanding of Fault models.
• 3. To understands test pattern generation techniques for fault detection.
• 4. To design fault diagnosis in sequential circuits.
• 5. To provide understanding in the design of flow using case studies.

UNIT - I

Programmable Logic Devices: The concept of programmable Logic Devices, SPLDs, PAL devices, PLA devices, GAL devices, CPLD-Architecture, FPGAs-FPGA technology, architecture, virtex CLB and slice, FPGA Programming Technologies, Xilinx XC2000, XC3000, XC4000 Architectures, Actel ACT1, ACT2 and ACT3 Architectures. [TEXTBOOK-1]

UNIT - II

Analysis and derivation of clocked sequential circuits with state graphs and tables: A sequential parity checker, Analysis by signal tracing and timing charts-state tables and graphs-general models for sequential circuits, Design of a sequence detector, More Complex design problems, Guidelines for construction of state graphs, serial data conversion, Alphanumeric state graph notation. Need and Design stratagies for multi-clock sequential circuits. [TEXTBOOK-2]

UNIT - III

Sequential circuit Design: Design procedure for sequential circuits-design example, Code converter, Design of Iterative circuits, Design of a comparator, Controller (FSM) – Metastability, Synchronozation, FSM Issues, Pipelining resources sharing, Sequential circuit design using FPGAs, Simulation and testing of Sequential circuits, Overview of computer Aided Design. [TEXTBOOK-2]

UNIT - IV

Fault Modeling and Test Pattern Generation: Logic Fault Model, Fault detection & redundancy, Fault equivalence and fault location, Fault dominance, Single stuck at fault model, multiple Stuck at Fault models, Bridging Fault model. Fault diagnosis of combinational circuits by conventional methods, path sensitization techniques, Boolean difference method, KOHAVI algorithm, Test algorithms-D algorithm, Random testing, transition count testing, signature analysis and test bridging faults. [TEXTBOOK-3 & Ref.1]

UNIT - V

Fault Diagnosis in sequential circuits: Circuit Test Approach, Transition check Approach, State identification and fault detection experiment, Machine identification, Design of fault detection experiment. [Ref.3]

TEXT BOOKS:

• 1. Digital Electronics and design with VHDL- Volnei A. Pedroni, Elsevier publications.
• 2. Fundamentals of Logic Design-Charles H.Roth,Jr. -5thEd.,Cengage Learning.
• 3. Digital Circuits and Logic Design-Samuel C.LEE,PHI, 2008.

REFERENCE BOOKS:

• 1. Logic Design Theory-N.N.Biswas,PHI.
• 2. Digital System Design using programmable logic devices- Parag K.Lala, BS publications.
• 3. Switching and Finite Automata Theory - Zvi Kohavi & Niraj K. Jha, 3rd Edition, Cambridge, 2010. M.TECH.- I YEAR- I SEMESTER DIGITAL SYSTEMS & COMPUTER ELECTRONICS