JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

Course Objectives:

• 1. To Learn System Verilog for Verification constructs.
• 2. To understand the UVM methodology.
• 3. To know UVM implementation for Verilog RTLs.

Course Outcomes

Students will be able to:

• 1. Implement test bench programs using system Verilog.
• 2. Develop random stimulus and SVAs using system Verilog.
• 3. Develop a UVM testbench with all its features.

UNIT - I

Verification Basics: Introduction, Verification need, Test bench components, Directed versus random stimulus, Code coverage versus functional coverage, Types of code coverage, Verification plan and test plan.

UNIT - II

System Verilog – I: Introduction, Constructs, Interface and object-oriented programming concepts.

UNIT - III

System Verilog – II: Randomization, Functional coverage and system verilog assertions.

UNIT - IV

UVM Test Bench Architecture: Introduction, UVM components and UVM phases.

UNIT - V

UVM Methodology: UVM component configuration and factory, Modelling UVM transactions, UVM sequence, Virtual sequencer, Component communication and UVM reporting.

TEXT BOOKS:

• 1. Janic Bergeron, "Writing Testbenches: Functional Verification of HDL Models", 2nd Ed., Kluwer Academic Publishers, 2003.
• 2. Stuart Sutherland, Simon Davidmann and Peter Flake, "System Verilog for Design", 2nd Ed., Springer, 2006.

REFERENCE BOOK:

• 1. Reference Verification Methodology User Guide, Version 8.5.11 – Synopsis M.TECH. - I YEAR- II SEMESTER VLSI/VLSI DESIGN/VLSI SYSTEM DESIGN